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From: Richard Sandiford <richard.sandiford@arm.com>
To: Jonathan Wright via Gcc-patches <gcc-patches@gcc.gnu.org>
Mail-Followup-To: Jonathan Wright via Gcc-patches <gcc-patches@gcc.gnu.org>,
 Jonathan Wright <Jonathan.Wright@arm.com>, richard.sandiford@arm.com
Subject: Re: [PATCH 16/20] aarch64: Relax aarch64_<sur><addsub>hn2<mode> RTL
 pattern
References: <DBBPR08MB4758EA3D5E82073F97309CE4EB409@DBBPR08MB4758.eurprd08.prod.outlook.com>
Date: Wed, 28 Apr 2021 16:57:22 +0100
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 (Jonathan Wright via Gcc-patches's message of "Wed, 28 Apr 2021
 14:53:34 +0000")
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Jonathan Wright via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> Hi,
>
> As subject, this patch implements the v[r]addhn2 and v[r]subhn2 Neon
> intrinsic RTL patterns using a vec_concat of a register_operand and an
> ADDSUBHN unspec - instead of just an ADDSUBHN2 unspec. This more
> relaxed pattern allows for more aggressive combinations and ultimately
> better code generation.

With this and patch 17, it would be good to have some tests that
show (and defend) the improvement.

Thanks,
Richard

>
> Regression tested and bootstrapped on aarch64-none-linux-gnu and
> aarch64_be-none-elf - no issues.
>
> Ok for master?
>
> Thanks,
> Jonathan
>
> ---
>
> gcc/ChangeLog:
>
> 2021-03-03 =C2=A0Jonathan Wright =C2=A0<jonathan.wright@arm.com>
>
> 	* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>):
> 	Implement as an expand emitting a big/little endian
> 	instruction pattern.
> 	(aarch64_<sur><addsub>hn2<mode>_insn_le): Define.
> 	(aarch64_<sur><addsub>hn2<mode>_insn_be): Define.