From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id E2951385782B for ; Mon, 21 Nov 2022 12:17:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E2951385782B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C1091FB; Mon, 21 Nov 2022 04:17:29 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DE0803F587; Mon, 21 Nov 2022 04:17:21 -0800 (PST) From: Richard Sandiford To: "Andre Vieira \(lists\)" Mail-Followup-To: "Andre Vieira \(lists\)" ,Kyrylo Tkachov , "gcc-patches\@gcc.gnu.org" , Richard Earnshaw , richard.sandiford@arm.com Cc: Kyrylo Tkachov , "gcc-patches\@gcc.gnu.org" , Richard Earnshaw Subject: Re: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions References: <0f0f4ffc-daa9-7b4d-334b-3941596a86cf@arm.com> Date: Mon, 21 Nov 2022 12:17:20 +0000 In-Reply-To: (Andre Vieira's message of "Fri, 18 Nov 2022 13:41:19 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-40.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: "Andre Vieira (lists)" writes: > Sorry for the late reply on this. I was wondering though why the check > made sense. The way I see it, SI -> SI mode is either wrong or useless. > So why not: > if it is wrong, error (gcc_assert?) so we know it was generated wrongly > somehow and fix it; > if it is useless, still use this pattern as we avoid an extra > instruction (doing useless work). The comparison doesn't lead to extra instructions. It's a compile-time constant, so the invalid patterns will be automatically dropped and not result in any code. That is, having the condition reduces the amount of static data (fewer patterns means fewer data structures for them) and reduces the code size (less for recog to do). If we want an assert for invalid extensions (which might be a good thing), it should be in target-independent code, so that it triggers regardless of whether the target defines a (bogus) pattern for it. Thanks, Richard > > Unless, you expect the backend to be 'probing' for this and the way we > tell it not to is to not implement any pattern that allows for this? But > somehow that doesn't feel like the right approach... > > On 17/11/2022 11:30, Kyrylo Tkachov wrote: >> >>> -----Original Message----- >>> From: Richard Sandiford >>> Sent: Tuesday, November 15, 2022 6:05 PM >>> To: Andre Simoes Dias Vieira >>> Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; >>> Richard Earnshaw >>> Subject: Re: [PATCH 2/2] aarch64: Add support for widening LDAPR >>> instructions >>> >>> "Andre Vieira (lists)" writes: >>>> Updated version of the patch to account for the testsuite changes in the >>>> first patch. >>>> >>>> On 10/11/2022 11:20, Andre Vieira (lists) via Gcc-patches wrote: >>>>> Hi, >>>>> >>>>> This patch adds support for the widening LDAPR instructions. >>>>> >>>>> Bootstrapped and regression tested on aarch64-none-linux-gnu. >>>>> >>>>> OK for trunk? >>>>> >>>>> 2022-11-09 Andre Vieira >>>>> Kyrylo Tkachov >>>>> >>>>> gcc/ChangeLog: >>>>> >>>>> * config/aarch64/atomics.md >>>>> (*aarch64_atomic_load_rcpc_zext): New pattern. >>>>> (*aarch64_atomic_load_rcpc_zext): Likewise. >>>>> >>>>> gcc/testsuite/ChangeLog: >>>>> >>>>> * gcc.target/aarch64/ldapr-ext.c: New test. >>>> diff --git a/gcc/config/aarch64/atomics.md >>> b/gcc/config/aarch64/atomics.md >>>> index >>> dc5f52ee8a4b349c0d8466a16196f83604893cbb..9670bef7d8cb2b32c5146536 >>> d806a7e8bdffb2e3 100644 >>>> --- a/gcc/config/aarch64/atomics.md >>>> +++ b/gcc/config/aarch64/atomics.md >>>> @@ -704,6 +704,28 @@ >>>> } >>>> ) >>>> >>>> +(define_insn "*aarch64_atomic_load_rcpc_zext" >>>> + [(set (match_operand:GPI 0 "register_operand" "=r") >>>> + (zero_extend:GPI >>>> + (unspec_volatile:ALLX >>>> + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") >>>> + (match_operand:SI 2 "const_int_operand")] ;; >>> model >>>> + UNSPECV_LDAP)))] >>>> + "TARGET_RCPC" >>>> + "ldapr\t%0, %1" >>> It would be good to add: >>> >>> > >>> >>> to the condition, so that we don't provide bogus SI->SI and DI->DI >>> extensions. (They shouldn't be generated, but it's better not to provide >>> them anyway.) >>> >> I agree. I'm pushing the attached patch to trunk. >> >> gcc/ChangeLog: >> >> * config/aarch64/atomics.md (*aarch64_atomic_load_rcpc_zext): >> Add mode size check to condition. >> (*aarch64_atomic_load_rcpc_sext): Likewise. >> >>> Thanks, >>> Richard >>> >>>> +) >>>> + >>>> +(define_insn "*aarch64_atomic_load_rcpc_sext" >>>> + [(set (match_operand:GPI 0 "register_operand" "=r") >>>> + (sign_extend:GPI >>>> + (unspec_volatile:ALLX >>>> + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") >>>> + (match_operand:SI 2 "const_int_operand")] ;; >>> model >>>> + UNSPECV_LDAP)))] >>>> + "TARGET_RCPC" >>>> + "ldaprs\t%0, %1" >>>> +) >>>> + >>>> (define_insn "atomic_store" >>>> [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust") >>>> (unspec_volatile:ALLI >>>> diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c >>> b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c >>>> new file mode 100644 >>>> index >>> 0000000000000000000000000000000000000000..aed27e06235b1d266decf11 >>> 745dacf94cc59e76d >>>> --- /dev/null >>>> +++ b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c >>>> @@ -0,0 +1,94 @@ >>>> +/* { dg-do compile } */ >>>> +/* { dg-options "-O2 -std=c99" } */ >>>> +/* { dg-final { check-function-bodies "**" "" "" } } */ >>>> +#include >>>> + >>>> +#pragma GCC target "+rcpc" >>>> + >>>> +atomic_ullong u64; >>>> +atomic_llong s64; >>>> +atomic_uint u32; >>>> +atomic_int s32; >>>> +atomic_ushort u16; >>>> +atomic_short s16; >>>> +atomic_uchar u8; >>>> +atomic_schar s8; >>>> + >>>> +#define TEST(name, ldsize, rettype) \ >>>> +rettype \ >>>> +test_##name (void) \ >>>> +{ \ >>>> + return atomic_load_explicit (&ldsize, memory_order_acquire); \ >>>> +} >>>> + >>>> +/* >>>> +**test_u8_u64: >>>> +**... >>>> +** ldaprb x0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(u8_u64, u8, unsigned long long) >>>> + >>>> +/* >>>> +**test_s8_s64: >>>> +**... >>>> +** ldaprsb x0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(s8_s64, s8, long long) >>>> + >>>> +/* >>>> +**test_u16_u64: >>>> +**... >>>> +** ldaprh x0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(u16_u64, u16, unsigned long long) >>>> + >>>> +/* >>>> +**test_s16_s64: >>>> +**... >>>> +** ldaprsh x0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(s16_s64, s16, long long) >>>> + >>>> +/* >>>> +**test_u8_u32: >>>> +**... >>>> +** ldaprb w0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(u8_u32, u8, unsigned) >>>> + >>>> +/* >>>> +**test_s8_s32: >>>> +**... >>>> +** ldaprsb w0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(s8_s32, s8, int) >>>> + >>>> +/* >>>> +**test_u16_u32: >>>> +**... >>>> +** ldaprh w0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(u16_u32, u16, unsigned) >>>> + >>>> +/* >>>> +**test_s16_s32: >>>> +**... >>>> +** ldaprsh w0, \[x[0-9]+\] >>>> +** ret >>>> +*/ >>>> + >>>> +TEST(s16_s32, s16, int)