From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EFA9C3858C52 for ; Fri, 23 Sep 2022 14:01:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EFA9C3858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19C3F139F; Fri, 23 Sep 2022 07:01:31 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75D673F73B; Fri, 23 Sep 2022 07:01:23 -0700 (PDT) From: Richard Sandiford To: Tamar Christina Mail-Followup-To: Tamar Christina ,"gcc-patches\@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov , rguenther@suse.de, richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov , rguenther@suse.de Subject: Re: [PATCH 2/2]AArch64 Add support for neg on v1df References: Date: Fri, 23 Sep 2022 15:01:22 +0100 In-Reply-To: (Tamar Christina's message of "Fri, 23 Sep 2022 10:10:01 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-47.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tamar Christina writes: >> -----Original Message----- >> From: Richard Sandiford >> Sent: Friday, September 23, 2022 6:04 AM >> To: Tamar Christina >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw >> ; Marcus Shawcroft >> ; Kyrylo Tkachov >> Subject: Re: [PATCH 2/2]AArch64 Add support for neg on v1df >>=20 >> Tamar Christina writes: >> >> -----Original Message----- >> >> From: Richard Sandiford >> >> Sent: Friday, September 23, 2022 5:30 AM >> >> To: Tamar Christina >> >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw >> >> ; Marcus Shawcroft >> >> ; Kyrylo Tkachov >> >> >> Subject: Re: [PATCH 2/2]AArch64 Add support for neg on v1df >> >> >> >> Tamar Christina writes: >> >> > Hi All, >> >> > >> >> > This adds support for using scalar fneg on the V1DF type. >> >> > >> >> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. >> >> > >> >> > Ok for master? >> >> >> >> Why just this one operation though? Couldn't we extend iterators >> >> like >> >> GPF_F16 to include V1DF, avoiding the need for new patterns? >> >> >> > >> > Simply because it's the only one I know how to generate code for. >> > I can change GPF_F16 but I don't know under which circumstances we'd >> > generate a V1DF for the other operations. >>=20 >> We'd do it for things like: >>=20 >> __Float64x1_t foo (__Float64x1_t x) { return -x; } >>=20 >> if the pattern is available, instead of using subregs. So one way would= be to >> scan the expand rtl dump for subregs. > > Ahh yes, I forgot about that ACLE type. > >>=20 >> If the point is that there is no observable difference between defining = 1- >> element vector ops and not, except for this one case, then that suggests= we >> should handle this case in target-independent code instead. There's no = point >> forcing every target that has V1DF to define a duplicate of the DF neg >> pattern. > > My original approach was to indeed use DF instead of V1DF, however since = we > do define V1DF I had expected the mode to be somewhat usable. > > So I'm happy to do whichever one you prefer now that I know how to test i= t. > I can either change my mid-end code, or extend the coverage of V1DF, any = preference? =F0=9F=98=8A I don't mind really, as long as we're consistent. Maybe Richi has an opini= on. If he doesn't mind either, then I guess it makes sense to define the ops as completely as possible (e.g. equivalently to V2SF), although it doesn't need to be all in one go. Thanks, Richard > Tamar > >>=20 >> Thanks, >> Richard >> > >> > So if it's ok to do so without full test coverage I'm happy to do so... >> > >> > Tamar. >> > >> >> Richard >> >> >> >> > >> >> > Thanks, >> >> > Tamar >> >> > >> >> > gcc/ChangeLog: >> >> > >> >> > * config/aarch64/aarch64-simd.md (negv1df2): New. >> >> > >> >> > gcc/testsuite/ChangeLog: >> >> > >> >> > * gcc.target/aarch64/simd/addsub_2.c: New test. >> >> > >> >> > --- inline copy of patch -- >> >> > diff --git a/gcc/config/aarch64/aarch64-simd.md >> >> > b/gcc/config/aarch64/aarch64-simd.md >> >> > index >> >> > >> >> >> f4152160084d6b6f34bd69f0ba6386c1ab50f77e..cf8c094bd4b76981cef2dd5dd7 >> >> b8 >> >> > e6be0d56101f 100644 >> >> > --- a/gcc/config/aarch64/aarch64-simd.md >> >> > +++ b/gcc/config/aarch64/aarch64-simd.md >> >> > @@ -2713,6 +2713,14 @@ (define_insn "neg2" >> >> > [(set_attr "type" "neon_fp_neg_")] >> >> > ) >> >> > >> >> > +(define_insn "negv1df2" >> >> > + [(set (match_operand:V1DF 0 "register_operand" "=3Dw") >> >> > + (neg:V1DF (match_operand:V1DF 1 "register_operand" "w")))] >> >> > +"TARGET_SIMD" >> >> > + "fneg\\t%d0, %d1" >> >> > + [(set_attr "type" "neon_fp_neg_d")] >> >> > +) >> >> > + >> >> > (define_insn "abs2" >> >> > [(set (match_operand:VHSDF 0 "register_operand" "=3Dw") >> >> > (abs:VHSDF (match_operand:VHSDF 1 "register_operand" >> >> > "w")))] diff --git >> >> > a/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> >> > b/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> >> > new file mode 100644 >> >> > index >> >> > >> >> >> 0000000000000000000000000000000000000000..55a7365e897f8af509de953129 >> >> e0 >> >> > f516974f7ca8 >> >> > --- /dev/null >> >> > +++ b/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> >> > @@ -0,0 +1,22 @@ >> >> > +/* { dg-do compile } */ >> >> > +/* { dg-options "-Ofast" } */ >> >> > +/* { dg-final { check-function-bodies "**" "" "" { target { le } } >> >> > +} } */ >> >> > + >> >> > +#pragma GCC target "+nosve" >> >> > + >> >> > +/* >> >> > +** f1: >> >> > +** ... >> >> > +** fneg d[0-9]+, d[0-9]+ >> >> > +** fadd v[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s >> >> > +** ... >> >> > +*/ >> >> > +void f1 (float *restrict a, float *restrict b, float *res, int n) { >> >> > + for (int i =3D 0; i < 2; i+=3D2) >> >> > + { >> >> > + res[i+0] =3D a[i+0] + b[i+0]; >> >> > + res[i+1] =3D a[i+1] - b[i+1]; >> >> > + } >> >> > +} >> >> > +