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From: Richard Sandiford <richard.sandiford@arm.com>
To: Zhongyunde <zhongyunde@huawei.com>
Cc: "gcc-patches\@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
	"Yangfei \(A\)" <lancelo.yang@huawei.com>
Subject: Re: 答复: [PATCH PR95696] regrename creates overlapping register allocations for vliw
Date: Tue, 21 Jul 2020 17:12:10 +0100	[thread overview]
Message-ID: <mptlfjcvodh.fsf@arm.com> (raw)
In-Reply-To: <3077AC2A5F43A1418280D802C4B7FC117370F585@dggemm508-mbx.china.huawei.com> (Zhongyunde's message of "Tue, 21 Jul 2020 07:20:59 +0000")

Zhongyunde <zhongyunde@huawei.com> writes:
> Thanks for your review.
>
> First of all, this is an optimization.

OK, good.

>    gcc do sms before reload, and here each insn use pseudo-register. After reload, they are allocated hard-register, then the regrename pass try to adjust the register number with def/use chain created by build_def_use.
>  As now gcc doesn't consider the VLIW bundles, so regrename pass may updated a reg which may not really unused, which will bring in invalid VLIW bundles. 
>    Before the final schedule, we usually recheck the validation of VLIW bundles, and reschedule the conflicted insns into two VLIW to make them validation to avoid above issue, so this is not a correctness issue. 
>  Certainly, reschedule the conflicted insns into two VLIW will destroy the kernel loop's sms schedule result, and usually it will be harmful to the performance.

Yeah.  The reason I was worried about the TI markers being stale is
that, in general, register allocation can introduce new spills and
reloads, can add and remove instructions, and can convert instructions
into different forms (e.g. as a result of register elimination).
There are then post-reload optimisers that can change the code further.
All these things could invalidate the VLIW bundling done by the first
scheduler.

It sounds like that's not happening in your motivating testcase, and the
VLIW bundling is still correct (for this loop) by the time that regrename
runs.  Is that right?

It's interesting that this is for a testcase using SMS.  One of the
traditional problems with the GCC implementation of SMS has been
ensuring that later passes don't mess up the scheduled loop.  So in your
testcase, does register allocation succeed for the SMS loop without
invalidating the bundling decisions?

If so, then it's probably better to avoid running regrename on it at all.
It mostly exists to help the second scheduling pass, but the second
scheduling pass shouldn't be messing with an SMS loop anyway.  Also,
although the patch deals with one case in which regrename could disrupt
the bundling, there are others too.

So maybe one option would be to make regrename ignore blocks that have
BB_DISABLE_SCHEDULE set.  (Sorry if that's been discussed and discounted
already.)

Thanks,
Richard

      reply	other threads:[~2020-07-21 16:12 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-16 16:18 zhongyunde
2020-07-20  0:59 ` Zhongyunde
2020-07-20 16:05   ` Richard Sandiford
2020-07-21  7:20     ` 答复: " Zhongyunde
2020-07-21 16:12       ` Richard Sandiford [this message]

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