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From: Richard Sandiford <richard.sandiford@arm.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: "Takayuki 'January June' Suwa" <jjsuwa_sys3175@yahoo.co.jp>,
	 gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 6/6] Add a late-combine pass [PR106594]
Date: Mon, 24 Jun 2024 09:03:45 +0100	[thread overview]
Message-ID: <mpto77qu5r2.fsf@arm.com> (raw)
In-Reply-To: <CAFiYyc3o7WAyNBToM6-_VWFOHe+_FSzJ5N6qQ2G9-Pf_qccCaQ@mail.gmail.com> (Richard Biener's message of "Sun, 23 Jun 2024 11:34:05 +0200")

Richard Biener <richard.guenther@gmail.com> writes:
> On Sat, Jun 22, 2024 at 6:50 PM Richard Sandiford
>> The traditional (and IMO correct) way to handle this is to make the
>> pattern reserve the temporary registers that it needs, using match_scratches.
>> rs6000 has many examples of this.  E.g.:
>>
>> (define_insn_and_split "@ieee_128bit_vsx_neg<mode>2"
>>   [(set (match_operand:IEEE128 0 "register_operand" "=wa")
>>         (neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
>>    (clobber (match_scratch:V16QI 2 "=v"))]
>>   "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
>>   "#"
>>   "&& 1"
>>   [(parallel [(set (match_dup 0)
>>                    (neg:IEEE128 (match_dup 1)))
>>               (use (match_dup 2))])]
>> {
>>   if (GET_CODE (operands[2]) == SCRATCH)
>>     operands[2] = gen_reg_rtx (V16QImode);
>>
>>   emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
>> }
>>   [(set_attr "length" "8")
>>    (set_attr "type" "vecsimple")])
>>
>> Before RA, this is just:
>>
>>   (set ...)
>>   (clobber (scratch:V16QI))
>>
>> and the split creates a new register.  After RA, operand 2 provides
>> the required temporary register:
>>
>>   (set ...)
>>   (clobber (reg:V16QI TMP))
>>
>> Another approach is to add can_create_pseudo_p () to the define_insn
>> condition (rather than the split condition).  But IMO that's an ICE
>> trap, since insns that have already been matched & accepted shouldn't
>> suddenly become invalid if recog is reattempted later.
>
> What about splitting immediately in late-combine?  Wouldn't that possibly
> allow more combinations to immediately happen?

It would be difficult to guarantee termination.  Often the split
instructions can be immediately recombined back to the original
instruction.  Even if we guard against that happening directly,
it'd be difficult to prove that it can't happen indirectly.

We might also run into issues like PR101523.

Combine uses define_splits (without define_insns) for 3->2 combinations,
but the current late-combine optimisation is kind-of 1/N+1->1 x N.

Personally, I think we should allow targets to use the .md file to
define match.pd-style simplification rules involving unspecs, but there
were objections to that when I last suggested it.

Thanks,
Richard

  reply	other threads:[~2024-06-24  8:03 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-20 13:34 [PATCH 0/6] Add a late-combine pass Richard Sandiford
2024-06-20 13:34 ` [PATCH 1/6] rtl-ssa: Rework _ignoring interfaces Richard Sandiford
2024-06-20 21:22   ` Alex Coplan
2024-06-21  8:11     ` Richard Sandiford
2024-06-21 14:40   ` Jeff Law
2024-06-20 13:34 ` [PATCH 2/6] rtl-ssa: Don't cost no-op moves Richard Sandiford
2024-06-21 14:32   ` Jeff Law
2024-06-20 13:34 ` [PATCH 3/6] iq2000: Fix test and branch instructions Richard Sandiford
2024-06-21 14:33   ` Jeff Law
2024-06-20 13:34 ` [PATCH 4/6] sh: Make *minus_plus_one work after RA Richard Sandiford
2024-06-21  0:15   ` Oleg Endo
2024-06-20 13:34 ` [PATCH 5/6] xstormy16: Fix xs_hi_nonmemory_operand Richard Sandiford
2024-06-21 14:33   ` Jeff Law
2024-06-20 13:34 ` [PATCH 6/6] Add a late-combine pass [PR106594] Richard Sandiford
2024-06-21  0:17   ` Oleg Endo
2024-06-21  8:09     ` Richard Sandiford
2024-06-21  5:54   ` Richard Biener
2024-06-21  8:21     ` Richard Sandiford
2024-06-21  9:26       ` Richard Biener
2024-06-21 15:00   ` Jeff Law
2024-06-22  5:12   ` Takayuki 'January June' Suwa
2024-06-22 16:49     ` Richard Sandiford
2024-06-23  4:40       ` Takayuki 'January June' Suwa
2024-06-23  9:34       ` Richard Biener
2024-06-24  8:03         ` Richard Sandiford [this message]
2024-06-24 11:22           ` Richard Biener
2024-06-24 11:34             ` Richard Sandiford
2024-06-24 12:18               ` Richard Biener
2024-06-25  9:02   ` Thomas Schwinge
2024-06-25  9:07     ` Richard Sandiford
2024-06-25  9:23       ` rs6000: Properly default-disable late-combine passes [PR106594, PR115622, PR115633] (was: [PATCH 6/6] Add a late-combine pass [PR106594]) Thomas Schwinge
2024-06-25  9:28         ` rs6000: Properly default-disable late-combine passes [PR106594, PR115622, PR115633] Richard Sandiford
2024-06-28 12:25 ` LoongArch vs. [PATCH 0/6] Add a late-combine pass Xi Ruoyao
2024-06-28 12:34   ` chenglulu
2024-06-28 12:35     ` Xi Ruoyao
2024-06-28 12:44       ` chenglulu

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