From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id CAE6C3858D1E for ; Tue, 7 Nov 2023 22:51:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CAE6C3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CAE6C3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699397501; cv=none; b=BMxZPka/jMYGDvJyPr/mV3DA4rOuf4nzCheg4IveJV0hRVp21TF3W0hu0X8B7TCWgTYC71DkO0W7CE57aDdI6QAS9H8at9iWZqWGUwObM+ocky3F2NMxrpzGXo0L16w9OovsczQA7dHFQuTJJcmgt5UzMNBaDeNdPF/qw2g2sms= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699397501; c=relaxed/simple; bh=qG0pYgCxHuyHdE8Tw8apQ458ZU4ldVh43JWRZAKgJj8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Smt/y1lRcLXbY1Ait2GWsNSDVFLaobq0Ss6T7qwYXuQtyMZezVP0wG80zQ/1TU0J5hBNDrtfSifQ62mr86CW6PNgJ7Ty+6J2QZ7lOoa6s9R2PQTQFdKOkwkrr7k2JWf7sMkfqeDs83P0C48j2qWmo7eblOZ144ToJY9/XCHWNWg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04FB31476; Tue, 7 Nov 2023 14:52:24 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BBD183F64C; Tue, 7 Nov 2023 14:51:38 -0800 (PST) From: Richard Sandiford To: Victor Do Nascimento Mail-Followup-To: Victor Do Nascimento ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests References: <20231107103211.2837188-1-victor.donascimento@arm.com> <20231107103211.2837188-6-victor.donascimento@arm.com> Date: Tue, 07 Nov 2023 22:51:37 +0000 In-Reply-To: <20231107103211.2837188-6-victor.donascimento@arm.com> (Victor Do Nascimento's message of "Tue, 7 Nov 2023 10:30:14 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-23.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Victor Do Nascimento writes: > Extend existing unit tests for the ACLE system register manipulation > functions to include 128-bit tests. > > gcc/testsuite/ChangeLog: > > * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New. > (set_wsr128): Likewise. > --- > gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c > index 3af4b960306..e7725022316 100644 > --- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c > +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c > @@ -1,11 +1,15 @@ > /* Test the __arm_[r,w]sr ACLE intrinsics family. */ > /* Check that function variants for different data types handle types correctly. */ > /* { dg-do compile } */ > -/* { dg-options "-O1 -march=armv8.4-a" } */ > +/* { dg-options "-O1 -march=armv9.4-a+d128" } */ > /* { dg-final { check-function-bodies "**" "" } } */ I'm nervous about having our only tests for 64-bit reads and writes using such a high minimum version. Could the file instead be compiled without any minimum architecture and have tests that work with plain -march=armv8-a? Then the test could switch to other architectures where necessary using #pragam GCC target. This test... > #include > > +#ifndef __ARM_FEATURE_SYSREG128 > +#error "__ARM_FEATURE_SYSREG128 feature macro not defined." > +#endif > + ...would still work. with a #pragma GCC target. Thanks, Richard > /* > ** get_rsr: > ** ... > @@ -66,6 +70,17 @@ get_rsrf64 () > return __arm_rsrf64("trcseqstr"); > } > > +/* > +** get_rsr128: > +** mrrs x0, x1, s3_0_c7_c4_0 > +** ... > +*/ > +__uint128_t > +get_rsr128 () > +{ > + __arm_rsr128("par_el1"); > +} > + > /* > ** set_wsr32: > ** ... > @@ -129,6 +144,18 @@ set_wsrf64(double a) > __arm_wsrf64("trcseqstr", a); > } > > +/* > +** set_wsr128: > +** ... > +** msrr s3_0_c7_c4_0, x0, x1 > +** ... > +*/ > +void > +set_wsr128 (__uint128_t c) > +{ > + __arm_wsr128 ("par_el1", c); > +} > + > /* > ** set_custom: > ** ... > @@ -142,3 +169,4 @@ void set_custom() > __uint64_t b = __arm_rsr64("S1_2_C3_C4_5"); > __arm_wsr64("S1_2_C3_C4_5", b); > } > +