From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A5C333858D38 for ; Sun, 17 Sep 2023 14:41:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A5C333858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A1E21FB; Sun, 17 Sep 2023 07:41:51 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8BBC83F59C; Sun, 17 Sep 2023 07:41:13 -0700 (PDT) From: Richard Sandiford To: Prathamesh Kulkarni Mail-Followup-To: Prathamesh Kulkarni ,Adhemerval Zanella , gcc Patches , richard.sandiford@arm.com Cc: Adhemerval Zanella , gcc Patches Subject: Re: [AArch64][testsuite] Adjust vect_copy_lane_1.c for new code-gen References: Date: Sun, 17 Sep 2023 15:41:12 +0100 In-Reply-To: (Prathamesh Kulkarni's message of "Wed, 13 Sep 2023 20:20:08 +0530") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-24.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Prathamesh Kulkarni writes: > Hi, > After 27de9aa152141e7f3ee66372647d0f2cd94c4b90, there's a following regression: > FAIL: gcc.target/aarch64/vect_copy_lane_1.c scan-assembler-times > ins\\tv0.s\\[1\\], v1.s\\[0\\] 3 > > This happens because for the following function from vect_copy_lane_1.c: > float32x2_t > __attribute__((noinline, noclone)) test_copy_lane_f32 (float32x2_t a, > float32x2_t b) > { > return vcopy_lane_f32 (a, 1, b, 0); > } > > Before 27de9aa152141e7f3ee66372647d0f2cd94c4b90, > it got lowered to following sequence in .optimized dump: > [local count: 1073741824]: > _4 = BIT_FIELD_REF ; > __a_5 = BIT_INSERT_EXPR ; > return __a_5; > > The above commit simplifies BIT_FIELD_REF + BIT_INSERT_EXPR > to vector permutation and now thus gets lowered to: > > [local count: 1073741824]: > __a_4 = VEC_PERM_EXPR ; > return __a_4; > > Since we give higher priority to aarch64_evpc_zip over aarch64_evpc_ins > in aarch64_expand_vec_perm_const_1, it now generates: > > test_copy_lane_f32: > zip1 v0.2s, v0.2s, v1.2s > ret > > Similarly for test_copy_lane_[us]32. Yeah, I suppose this choice is at least as good as INS. It has the advantage that the source and destination don't need to be tied. For example: int32x2_t f(int32x2_t a, int32x2_t b, int32x2_t c) { return vcopy_lane_s32 (b, 1, c, 0); } used to be: f: mov v0.8b, v1.8b ins v0.s[1], v2.s[0] ret but is now: f: zip1 v0.2s, v1.2s, v2.2s ret > The attached patch adjusts the tests to reflect the change in code-gen > and the tests pass. > OK to commit ? > > Thanks, > Prathamesh > > diff --git a/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c > index 2848be564d5..811dc678b92 100644 > --- a/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c > @@ -22,7 +22,7 @@ BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2) > BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) > BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) > BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) > -/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */ > +/* { dg-final { scan-assembler-times "zip1\\tv0.2s, v0.2s, v1.2s" 3 } } */ > BUILD_TEST (int64x1_t, int64x1_t, , , s64, 0, 0) > BUILD_TEST (uint64x1_t, uint64x1_t, , , u64, 0, 0) > BUILD_TEST (float64x1_t, float64x1_t, , , f64, 0, 0) OK, thanks. Richard