From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80226 invoked by alias); 5 Jul 2019 15:20:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80211 invoked by uid 89); 5 Jul 2019 15:20:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-5.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,MEDICAL_SUBJECT,SPF_PASS autolearn=ham version=3.3.1 spammy=UD:rs6000.md, rs6000md, rs6000.md, bb X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 05 Jul 2019 15:20:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB5EA28; Fri, 5 Jul 2019 08:20:39 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A5DD3F246; Fri, 5 Jul 2019 08:20:38 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org,dje.gcc@gmail.com, segher@kernel.crashing.org, richard.sandiford@arm.com Cc: dje.gcc@gmail.com, segher@kernel.crashing.org Subject: [08/11] [rs6000] Fix ambiguous .md attribute uses References: Date: Fri, 05 Jul 2019 15:22:00 -0000 In-Reply-To: (Richard Sandiford's message of "Fri, 05 Jul 2019 16:05:51 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2019-07/txt/msg00457.txt.bz2 This patch is part of a series that fixes ambiguous attribute uses in .md files, i.e. cases in which attributes didn't use to specify an iterator, and in which could have different values depending on the iterator chosen. No behavioural change -- produces the same code as before except for formatting and line numbers. 2019-07-05 Richard Sandiford gcc/ * config/rs6000/rs6000.md (*mov_update1): Explicitly use , , and rather than leaving the choice between SFDF and P implicit. (*mov_update2): Likewise. (*cmp_internal2): Explicitly use rather than leaving the choice betweem IBM128 and GPR implicit. (*fix_trunc2_mem): Explicitly use rather than leaving the choice between IEEE128 and QHSI implicit. (AltiVec define_peephole2s): Explicitly use rather than leaving the choice between ALTIVEC_DFORM and P implicit. * config/rs6000/vsx.md (*vsx_ext__fl_) (*vsx_ext__ufl_): Explicitly use rather than leaving the choice between FL_CONV and VSX_EXTRACT_I implicit. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md 2019-07-03 20:50:46.390316903 +0100 +++ gcc/config/rs6000/rs6000.md 2019-07-05 15:08:06.639145562 +0100 @@ -9312,14 +9312,14 @@ (define_insn "*movqi_update3" (set_attr "update" "yes") (set_attr "indexed" "yes,no")]) -(define_insn "*mov_update1" - [(set (match_operand:SFDF 3 "gpc_reg_operand" "=,") +(define_insn "*mov_update1" + [(set (match_operand:SFDF 3 "gpc_reg_operand" "=,") (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") (match_operand:P 2 "reg_or_short_operand" "r,I")))) (set (match_operand:P 0 "gpc_reg_operand" "=b,b") (plus:P (match_dup 1) (match_dup 2)))] "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (mode) + && (!avoiding_indexed_address_p (mode) || !gpc_reg_operand (operands[2], Pmode))" "@ lfux %3,%0,%2 @@ -9327,16 +9327,16 @@ (define_insn "*mov_update1" [(set_attr "type" "fpload") (set_attr "update" "yes") (set_attr "indexed" "yes,no") - (set_attr "size" "")]) + (set_attr "size" "")]) -(define_insn "*mov_update2" +(define_insn "*mov_update2" [(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") (match_operand:P 2 "reg_or_short_operand" "r,I"))) - (match_operand:SFDF 3 "gpc_reg_operand" ",")) + (match_operand:SFDF 3 "gpc_reg_operand" ",")) (set (match_operand:P 0 "gpc_reg_operand" "=b,b") (plus:P (match_dup 1) (match_dup 2)))] "TARGET_HARD_FLOAT && TARGET_UPDATE - && (!avoiding_indexed_address_p (mode) + && (!avoiding_indexed_address_p (mode) || !gpc_reg_operand (operands[2], Pmode))" "@ stfux %3,%0,%2 @@ -9344,7 +9344,7 @@ (define_insn "*mov_update2" [(set_attr "type" "fpstore") (set_attr "update" "yes") (set_attr "indexed" "yes,no") - (set_attr "size" "")]) + (set_attr "size" "")]) (define_insn "*movsf_update3" [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") @@ -11558,7 +11558,7 @@ (define_insn "*cmp_internal1" [(set_attr "type" "fpcompare") (set_attr "length" "12")]) -(define_insn_and_split "*cmp_internal2" +(define_insn_and_split "*cmp_internal2" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d") (match_operand:IBM128 2 "gpc_reg_operand" "d"))) @@ -11571,7 +11571,7 @@ (define_insn_and_split "*cmp_inter (clobber (match_scratch:DF 9 "=d")) (clobber (match_scratch:DF 10 "=d")) (clobber (match_scratch:GPR 11 "=b"))] - "TARGET_XL_COMPAT && FLOAT128_IBM_P (mode) + "TARGET_XL_COMPAT && FLOAT128_IBM_P (mode) && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" @@ -11595,10 +11595,14 @@ (define_insn_and_split "*cmp_inter const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); - operands[5] = simplify_gen_subreg (DFmode, operands[1], mode, hi_word); - operands[6] = simplify_gen_subreg (DFmode, operands[1], mode, lo_word); - operands[7] = simplify_gen_subreg (DFmode, operands[2], mode, hi_word); - operands[8] = simplify_gen_subreg (DFmode, operands[2], mode, lo_word); + operands[5] = simplify_gen_subreg (DFmode, operands[1], + mode, hi_word); + operands[6] = simplify_gen_subreg (DFmode, operands[1], + mode, lo_word); + operands[7] = simplify_gen_subreg (DFmode, operands[2], + mode, hi_word); + operands[8] = simplify_gen_subreg (DFmode, operands[2], + mode, lo_word); operands[12] = gen_label_rtx (); operands[13] = gen_label_rtx (); real_inf (&rv); @@ -13597,7 +13601,7 @@ (define_peephole2 new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; - operands[5] = change_address (mem, mode, new_addr); + operands[5] = change_address (mem, mode, new_addr); }) ;; Optimize cases were want to do a D-form store on ISA 2.06/2.07 from an @@ -13633,7 +13637,7 @@ (define_peephole2 new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; - operands[5] = change_address (mem, mode, new_addr); + operands[5] = change_address (mem, mode, new_addr); }) @@ -14073,7 +14077,7 @@ (define_insn_and_split "*fix_trunc< (any_fix:QHSI (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:QHSI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" "&& reload_completed" [(set (match_dup 2) Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md 2019-07-03 20:50:46.390316903 +0100 +++ gcc/config/rs6000/vsx.md 2019-07-05 15:08:06.639145562 +0100 @@ -3828,7 +3828,7 @@ (define_insn_and_split "*vsx_ext_")]) + [(set_attr "isa" "")]) (define_insn_and_split "*vsx_ext__ufl_" [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=wa") @@ -3851,7 +3851,7 @@ (define_insn_and_split "*vsx_ext_")]) + [(set_attr "isa" "")]) ;; V4SI/V8HI/V16QI set operation on ISA 3.0 (define_insn "vsx_set__p9"