From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 223D4384B0CB for ; Thu, 6 Oct 2022 10:07:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 223D4384B0CB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0DE96169C; Thu, 6 Oct 2022 03:07:43 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AACD3F792; Thu, 6 Oct 2022 03:07:35 -0700 (PDT) From: Richard Sandiford To: Philipp Tomsich Mail-Followup-To: Philipp Tomsich ,gcc-patches@gcc.gnu.org, Tamar Christina , Christoph Muellner , richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org, Tamar Christina , Christoph Muellner Subject: Re: [PATCH v2] aarch64: update Ampere-1 core definition References: <20221006092951.607412-1-philipp.tomsich@vrull.eu> Date: Thu, 06 Oct 2022 11:07:34 +0100 In-Reply-To: <20221006092951.607412-1-philipp.tomsich@vrull.eu> (Philipp Tomsich's message of "Thu, 6 Oct 2022 11:29:51 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-44.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Philipp Tomsich writes: > This brings the extensions detected by -mcpu=native on Ampere-1 systems > in sync with the defaults generated for -mcpu=ampere1. > > Note that some early kernel versions on Ampere1 may misreport the > presence of PAUTH and PREDRES (i.e., -mcpu=native will add 'nopauth' > and 'nopredres'). > > gcc/ChangeLog: > > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update > Ampere-1 core entry. > > Signed-off-by: Philipp Tomsich OK, thanks. > Ok for backport? Yeah. I'll try to backport the RCPC change soon -- think it would be best to get that in first. Richard > > Changes in v2: > - Removed explicit RCPC, as the feature is now implicitly included > in the 8.3 feature definition. > > gcc/config/aarch64/aarch64-cores.def | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def > index b50628d6b51..e9a4b622be0 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -69,7 +69,7 @@ AARCH64_CORE("thunderxt81", thunderxt81, thunderx, V8A, (CRC, CRYPTO), thu > AARCH64_CORE("thunderxt83", thunderxt83, thunderx, V8A, (CRC, CRYPTO), thunderx, 0x43, 0x0a3, -1) > > /* Ampere Computing ('\xC0') cores. */ > -AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (), ampere1, 0xC0, 0xac3, -1) > +AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1) > /* Do not swap around "emag" and "xgene1", > this order is required to handle variant correctly. */ > AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag, 0x50, 0x000, 3)