From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2BF6E385803F for ; Thu, 11 Nov 2021 10:38:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2BF6E385803F Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE16ED6E; Thu, 11 Nov 2021 02:38:43 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C6803F70D; Thu, 11 Nov 2021 02:38:43 -0800 (PST) From: Richard Sandiford To: Jonathan Wright Mail-Followup-To: Jonathan Wright , "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov Subject: Re: [PATCH] aarch64: Use type-qualified builtins for ADDV Neon intrinsics References: Date: Thu, 11 Nov 2021 10:38:41 +0000 In-Reply-To: (Jonathan Wright's message of "Thu, 11 Nov 2021 10:31:09 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Nov 2021 10:38:46 -0000 Jonathan Wright writes: > Hi, > > This patch declares unsigned type-qualified builtins and uses them to > implement the vector reduction Neon intrinsics. This removes the need > for many casts in arm_neon.h. > > Regression tested and bootstrapped on aarch64-none-linux-gnu - no > issues. > > Ok for master? > > Thanks, > Jonathan > > --- > > gcc/ChangeLog: > > 2021-11-09 Jonathan Wright > > * config/aarch64/aarch64-simd-builtins.def: Declare unsigned > builtins for vector reduction. > * config/aarch64/arm_neon.h (vaddv_u8): Use type-qualified > builtin and remove casts. > (vaddv_u16): Likewise. > (vaddv_u32): Likewise. > (vaddvq_u8): Likewise. > (vaddvq_u16): Likewise. > (vaddvq_u32): Likewise. > (vaddvq_u64): Likewise. OK, thanks. Richard > > diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def > index 7d6de6728cf7c63872e09850a394101f7abf21d4..35a099e1fb8dd1acb9e35583d1267df257d961b0 100644 > --- a/gcc/config/aarch64/aarch64-simd-builtins.def > +++ b/gcc/config/aarch64/aarch64-simd-builtins.def > @@ -513,6 +513,7 @@ > > /* Implemented by aarch64_reduc_plus_. */ > BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, NONE) > + BUILTIN_VDQ_I (UNOPU, reduc_plus_scal_, 10, NONE) > > /* Implemented by reduc__scal_ (producing scalar). */ > BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10, NONE) > diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h > index ab46897d784b81bec9654d87557640ca4c1e5681..3c03432b5b6c6cd0f349671366615925d38121e5 100644 > --- a/gcc/config/aarch64/arm_neon.h > +++ b/gcc/config/aarch64/arm_neon.h > @@ -9695,21 +9695,21 @@ __extension__ extern __inline uint8_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddv_u8 (uint8x8_t __a) > { > - return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v8qi_uu (__a); > } > > __extension__ extern __inline uint16_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddv_u16 (uint16x4_t __a) > { > - return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v4hi_uu (__a); > } > > __extension__ extern __inline uint32_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddv_u32 (uint32x2_t __a) > { > - return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v2si_uu (__a); > } > > __extension__ extern __inline int8_t > @@ -9744,28 +9744,28 @@ __extension__ extern __inline uint8_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddvq_u8 (uint8x16_t __a) > { > - return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v16qi_uu (__a); > } > > __extension__ extern __inline uint16_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddvq_u16 (uint16x8_t __a) > { > - return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v8hi_uu (__a); > } > > __extension__ extern __inline uint32_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddvq_u32 (uint32x4_t __a) > { > - return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v4si_uu (__a); > } > > __extension__ extern __inline uint64_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vaddvq_u64 (uint64x2_t __a) > { > - return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a); > + return __builtin_aarch64_reduc_plus_scal_v2di_uu (__a); > } > > __extension__ extern __inline float32_t