From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 7F8093858D38 for ; Wed, 22 Nov 2023 18:40:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7F8093858D38 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7F8093858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700678413; cv=none; b=WWJne155DsxfAVK40JfQrOdlxGWiw6Uexzn20dZiL/Ommgo90Rqi492ZMNFMMZWfpCBio/ehYOx5Kp653RzpmfdfEVE5jpEd62XqKtLoaPFM1pq7bqsNP0F8qFv+bn3nKwdDPjf8aG9+av/U36hgd7EQvPIrz+o7l5kTD99rQNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700678413; c=relaxed/simple; bh=jujWDcxp38Ye1ZTJ3GU8TpgS6xNFKs4A8brtyImn+aE=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=fnCVDpZrKRpxR8Lv4YtKEx0GC5KCi8cNJhLw0pAji8WXRPYQ5/5GnYLU4QTRZuukZddrG9WMH5tLoUoUaHnCPdPFbUtQs9gyPjYrjqKLbqhH3Ffs9Ka+OOTIM3nc0vy/nYVLaM/Fk//KfnC8kqk/l2F0vcyoz20eZkZt9QZOYVQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from foss.arm.com ([217.140.110.172]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5s8m-0005j3-7O for gcc-patches@gcc.gnu.org; Wed, 22 Nov 2023 13:40:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 437851042; Wed, 22 Nov 2023 10:40:13 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6445D3F73F; Wed, 22 Nov 2023 10:39:25 -0800 (PST) From: Richard Sandiford To: "Li\, Pan2" Mail-Followup-To: "Li\, Pan2" ,Richard Biener , "juzhe.zhong\@rivai.ai" , "Wang\, Yanzhang" , "kito.cheng\@gmail.com" , Jeff Law , "gcc-patches\@gcc.gnu.org" , richard.sandiford@arm.com Cc: Richard Biener , "juzhe.zhong\@rivai.ai" , "Wang\, Yanzhang" , "kito.cheng\@gmail.com" , Jeff Law , "gcc-patches\@gcc.gnu.org" Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when read < store References: <20231102031423.3751965-1-pan2.li@intel.com> <20231113032237.1379330-1-pan2.li@intel.com> Date: Wed, 22 Nov 2023 18:39:24 +0000 In-Reply-To: (Pan2 Li's message of "Wed, 22 Nov 2023 11:38:35 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=217.140.110.172; envelope-from=richard.sandiford@arm.com; helo=foss.arm.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9,RCVD_IN_DNSWL_MED=-2.3,SPF_HELO_NONE=0.001,SPF_PASS=-0.001,T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-16.7 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: "Li, Pan2" writes: >> It looks like Jeff approved the patch? > > Yes, just would like to double check the way of this patch is expected as= following the suggestion of Richard S. Yeah, it looks good to me, thanks. Richard > Pan > > -----Original Message----- > From: Richard Biener =20 > Sent: Wednesday, November 22, 2023 4:02 PM > To: Li, Pan2 > Cc: richard.sandiford@arm.com; juzhe.zhong@rivai.ai; Wang, Yanzhang ; kito.cheng@gmail.com; Jeff Law ; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when re= ad < store > > On Wed, Nov 22, 2023 at 3:30=E2=80=AFAM Li, Pan2 wrot= e: >> >> Hi Richard S, >> >> Thanks a lot for reviewing and comments. May I know is there any concern= or further comments for landing this patch to GCC-14? > > It looks like Jeff approved the patch? > > Richard. > >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:25 AM >> To: gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang ; kito= .cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com; Je= ff Law >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when r= ead < store >> >> Sorry for disturbing, looks I have a typo for Richard S's email address,= cc the right email address for awareness. >> >> Pan >> >> -----Original Message----- >> From: Li, Pan2 >> Sent: Wednesday, November 15, 2023 8:18 AM >> To: Jeff Law ; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang ; kito= .cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: RE: [PATCH v4] DSE: Allow vector type for get_stored_val when r= ead < store >> >> > I wouldn't try to handle that case unless we had actual evidence it was >> > useful to do so. Just wanted to point out that unlike pseudos we can >> > have multiple modes referencing the same memory location. >> >> Got the point here, thanks Jeff for emphasizing this, =F0=9F=98=89. >> >> Pan >> >> -----Original Message----- >> From: Jeff Law >> Sent: Tuesday, November 14, 2023 4:12 AM >> To: Li, Pan2 ; gcc-patches@gcc.gnu.org >> Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang ; kito= .cheng@gmail.com; richard.guenther@gmail.com; richard.sandiford@arm.com2 >> Subject: Re: [PATCH v4] DSE: Allow vector type for get_stored_val when r= ead < store >> >> >> >> On 11/12/23 20:22, pan2.li@intel.com wrote: >> > From: Pan Li >> > >> > Update in v4: >> > * Merge upstream and removed some independent changes. >> > >> > Update in v3: >> > * Take known_le instead of known_lt for vector size. >> > * Return NULL_RTX when gap is not equal 0 and not constant. >> > >> > Update in v2: >> > * Move vector type support to get_stored_val. >> > >> > Original log: >> > >> > This patch would like to allow the vector mode in the >> > get_stored_val in the DSE. It is valid for the read >> > rtx if and only if the read bitsize is less than the >> > stored bitsize. >> > >> > Given below example code with >> > --param=3Driscv-autovec-preference=3Dfixed-vlmax. >> > >> > vuint8m1_t test () { >> > uint8_t arr[32] =3D { >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> > }; >> > >> > return __riscv_vle8_v_u8m1(arr, 32); >> > } >> > >> > Before this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi sp,sp,-32 >> > addi a5,a5,%lo(.LANCHOR0) >> > li a3,32 >> > vl2re64.v v2,0(a5) >> > vsetvli zero,a3,e8,m1,ta,ma >> > vs2r.v v2,0(sp) <=3D=3D Unnecessary store to stack >> > vle8.v v1,0(sp) <=3D=3D Ditto >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > After this patch: >> > test: >> > lui a5,%hi(.LANCHOR0) >> > addi a5,a5,%lo(.LANCHOR0) >> > li a4,32 >> > addi sp,sp,-32 >> > vsetvli zero,a4,e8,m1,ta,ma >> > vle8.v v1,0(a5) >> > vs1r.v v1,0(a0) >> > addi sp,sp,32 >> > jr ra >> > >> > Below tests are passed within this patch: >> > * The risc-v regression test. >> > * The x86 bootstrap and regression test. >> > * The aarch64 regression test. >> > >> > PR target/111720 >> > >> > gcc/ChangeLog: >> > >> > * dse.cc (get_stored_val): Allow vector mode if read size is >> > less than or equal to stored size. >> > >> > gcc/testsuite/ChangeLog: >> > >> > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. >> > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. >> OK for the trunk. >> >> >> > >> >> > + else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) >> > + && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (stor= e_mode)) >> > + && targetm.modes_tieable_p (read_mode, store_mode)) >> > + read_reg =3D gen_lowpart (read_mode, copy_rtx (store_info->rhs)); >> > else >> > read_reg =3D extract_low_bits (read_mode, store_mode, >> > copy_rtx (store_info->rhs)); >> It may not matter, especially for RV, but we could possibly have a >> mixture of scalar and vector modes in the RTL. Say a vector store >> followed by a scalar read or vice-versa. >> >> I wouldn't try to handle that case unless we had actual evidence it was >> useful to do so. Just wanted to point out that unlike pseudos we can >> have multiple modes referencing the same memory location. >> >> Jeff