From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A67623858C00 for ; Wed, 7 Sep 2022 09:53:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A67623858C00 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 853341042 for ; Wed, 7 Sep 2022 02:53:53 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C1F13F7B4 for ; Wed, 7 Sep 2022 02:54:15 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Prevent FPR register asms for +nofp Date: Wed, 07 Sep 2022 10:53:45 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-49.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: +nofp disabled the automatic allocation of FPRs, but it didn't stop users from explicitly putting register variables in FPRs. We'd then either report an ICE or generate unsupported instructions. It's still possible (and deliberately redundant) to specify FPRs in clobber lists. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_conditional_register_usage): Disallow use of FPRs in register asms for !TARGET_FLOAT. gcc/testsuite/ * gcc.target/aarch64/nofp_2.c: New test. --- gcc/config/aarch64/aarch64.cc | 1 + gcc/testsuite/gcc.target/aarch64/nofp_2.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/nofp_2.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 566763ce50c..786ede76131 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -19847,6 +19847,7 @@ aarch64_conditional_register_usage (void) { fixed_regs[i] = 1; call_used_regs[i] = 1; + CLEAR_HARD_REG_BIT (operand_reg_set, i); } } if (!TARGET_SVE) diff --git a/gcc/testsuite/gcc.target/aarch64/nofp_2.c b/gcc/testsuite/gcc.target/aarch64/nofp_2.c new file mode 100644 index 00000000000..8a262cc76fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/nofp_2.c @@ -0,0 +1,19 @@ +/* { dg-options "" } */ + +#pragma GCC target "+nothing+nofp" + +void +test (void) +{ + register int q0 asm ("q0"); // { dg-error "not general enough" } + register int q1 asm ("q1"); // { dg-error "not general enough" } + asm volatile ("" : "=w" (q0)); + q1 = q0; + asm volatile ("" :: "w" (q1)); +} + +void +ok (void) +{ + asm volatile ("" ::: "q0"); +} -- 2.25.1