From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 286A13857C5B for ; Thu, 11 Jan 2024 13:08:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 286A13857C5B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 286A13857C5B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704978495; cv=none; b=oiP4aNr5dPggo0O2LckOeN7XIMZrWc3AhrYBB1/UrETEhajY+smANFi98k7a8WGUWKdsTLOiw9I7q//ydfzwKYrKZiVgZfnxkX2KJ5AYz0T01+JuuzgsNaiH2yTSiICN8Fb9OfnYydy0g2HwdUM5RHdIDn+/rJcW6JfRqEBL8Os= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704978495; c=relaxed/simple; bh=jgCfbSQYcf/qszCJQPAqKtofNWlSzeLUDmslcxHghHU=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Icoda95ia7mQ3n2Ii+3cqbI4XXafLMTaEfMrwK0Zx/ZZFQLBrdwveowar3BNHd8McLnxQptgNc9emHVB4uIoPeCeePDEp9QhAYZVmajJUiSU9tsBWoOehwgYUACRjvKgsOWx17lL0tN/qWEBiq50KvC/YL7u4njY0RyPnJBcq3k= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6D932F4; Thu, 11 Jan 2024 05:08:57 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 41F0B3F73F; Thu, 11 Jan 2024 05:08:11 -0800 (PST) From: Richard Sandiford To: Radek Barton Mail-Followup-To: Radek Barton ,"gcc-patches\@gcc.gnu.org" , "pinskia\@gmail.com" , "10walls\@gmail.com" <10walls@gmail.com>, richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , "pinskia\@gmail.com" , "10walls\@gmail.com" <10walls@gmail.com> Subject: Re: [RFC] Either fix or disable SME feature for `aarch64-w64-mingw32` target? References: Date: Thu, 11 Jan 2024 13:08:10 +0000 In-Reply-To: (Radek Barton's message of "Tue, 9 Jan 2024 19:37:49 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-20.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,KAM_STOCKGEN,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Radek Barton writes: > Hello. > > I forgot to add the target maintainers to the CC. My apologies for that. > > Furthermore, I am adding also relevant changes in `libgcc/config/aarch64/lse.S` file to the patch. Originally we wanted to submit those changes separately but after the feedback from Andrew Pinski, it makes sense to add them here. I needed to rename `HIDDEN`, `TYPE`, and `SIZE` macros to `HIDDEN_PO`, `TYPE_PO`, and `SIZE_PO` (pseudo-op) because there is a collision with other macro named `SIZE` in the `lse.S` file. How about avoiding the clash by using the names HIDDEN, SYMBOL_TYPE and SYMBOL_SIZE, with SYMBOL_TYPE taking the symbol type as argument? What's the practical effect of not marking the symbols as hidden on mingw32? Will they still be local to the DLL/EXE, since they haven't been explicitly exported? (Sorry for the probably dumb question.) SME support for mingw32 will be limited until __aarch64_have_sme.c is ported to Windows. Until then, __aarch64_have_sme will just reflect the --with-cpu/arch default. But that obviously doesn't need to be fixed at the same time, just saying for the record. Thanks, Richard > > Best regards, > > Radek > > From eb30feb218f122db8d8d8970e7e1d6d1514ab6c4 Mon Sep 17 00:00:00 2001 > In-Reply-To: > References: > From: Zac Walker > Date: Wed, 3 Jan 2024 20:21:04 +0100 > Subject: [PATCH v3] Ifdef `.hidden`, `.type`, and `.size` pseudo-ops for > `aarch64-w64-mingw32` target > Cc: Andrew Pinski , > Richard Sandiford , > Jonathan Yong <10walls@gmail.com> > > Recent change (https://gcc.gnu.org/pipermail/gcc-cvs/2023-December/394915.html) added a generic SME support using `.hidden`, `.type`, and ``.size` pseudo-ops in the assembly sources, `aarch64-w64-mingw32` does not support the pseudo-ops though. This patch wraps usage of those pseudo-ops using macros and ifdefs them for `__ELF__` define. > --- > libgcc/config/aarch64/__arm_sme_state.S | 2 +- > libgcc/config/aarch64/__arm_tpidr2_save.S | 4 ++-- > libgcc/config/aarch64/__arm_za_disable.S | 6 +++--- > libgcc/config/aarch64/aarch64-asm.h | 14 ++++++++++++-- > libgcc/config/aarch64/crti.S | 12 ++++-------- > libgcc/config/aarch64/lse.S | 9 +++++---- > 6 files changed, 27 insertions(+), 20 deletions(-) > > diff --git a/libgcc/config/aarch64/__arm_sme_state.S b/libgcc/config/aarch64/__arm_sme_state.S > index 0da9b585b6c..8658da5dfa7 100644 > --- a/libgcc/config/aarch64/__arm_sme_state.S > +++ b/libgcc/config/aarch64/__arm_sme_state.S > @@ -30,7 +30,7 @@ > - Takes no argument. > - Returns SME state in x0 and TPIDR2_EL0 in x1. */ > > -.hidden __aarch64_have_sme > +HIDDEN_PO (__aarch64_have_sme) > > variant_pcs (__arm_sme_state) > > diff --git a/libgcc/config/aarch64/__arm_tpidr2_save.S b/libgcc/config/aarch64/__arm_tpidr2_save.S > index 9135cba1ddb..739694ed189 100644 > --- a/libgcc/config/aarch64/__arm_tpidr2_save.S > +++ b/libgcc/config/aarch64/__arm_tpidr2_save.S > @@ -31,7 +31,7 @@ > - Does not return a value. > - Can abort on failure (then registers are not preserved). */ > > -.hidden __aarch64_have_sme > +HIDDEN_PO (__aarch64_have_sme) > > variant_pcs (__arm_tpidr2_save) > > @@ -97,5 +97,5 @@ END (__arm_tpidr2_save) > > /* Hidden alias used by __arm_za_disable. */ > .global __libgcc_arm_tpidr2_save > -.hidden __libgcc_arm_tpidr2_save > +HIDDEN_PO (__libgcc_arm_tpidr2_save) > .set __libgcc_arm_tpidr2_save, __arm_tpidr2_save > diff --git a/libgcc/config/aarch64/__arm_za_disable.S b/libgcc/config/aarch64/__arm_za_disable.S > index 5785a959e22..95eae3ea958 100644 > --- a/libgcc/config/aarch64/__arm_za_disable.S > +++ b/libgcc/config/aarch64/__arm_za_disable.S > @@ -31,9 +31,9 @@ > - Does not return a value. > - Can abort on failure (then registers are not preserved). */ > > -.hidden __aarch64_have_sme > +HIDDEN_PO (__aarch64_have_sme) > > -.hidden __libgcc_arm_tpidr2_save > +HIDDEN_PO (__libgcc_arm_tpidr2_save) > > variant_pcs (__arm_za_disable) > > @@ -66,5 +66,5 @@ END (__arm_za_disable) > > /* Hidden alias used by the unwinder. */ > .global __libgcc_arm_za_disable > -.hidden __libgcc_arm_za_disable > +HIDDEN_PO (__libgcc_arm_za_disable) > .set __libgcc_arm_za_disable, __arm_za_disable > diff --git a/libgcc/config/aarch64/aarch64-asm.h b/libgcc/config/aarch64/aarch64-asm.h > index 24568429b5c..dbb81b4be6b 100644 > --- a/libgcc/config/aarch64/aarch64-asm.h > +++ b/libgcc/config/aarch64/aarch64-asm.h > @@ -58,6 +58,16 @@ > # define AUTIASP > #endif > > +#ifdef __ELF__ > +#define TYPE_PO(x) .type x,function > +#define HIDDEN_PO(x) .hidden x > +#define SIZE_PO(x) .size x, .-x > +#else > +#define TYPE_PO(x) > +#define HIDDEN_PO(x) > +#define SIZE_PO(x) > +#endif > + > /* Add a NT_GNU_PROPERTY_TYPE_0 note. */ > #define GNU_PROPERTY(type, value) \ > .section .note.gnu.property, "a"; \ > @@ -85,7 +95,7 @@ GNU_PROPERTY (FEATURE_1_AND, BTI_FLAG|PAC_FLAG) > > #define ENTRY_ALIGN(name, align) \ > .global name; \ > - .type name,%function; \ > + TYPE_PO(name); \ > .balign align; \ > name: \ > .cfi_startproc; \ > @@ -95,4 +105,4 @@ GNU_PROPERTY (FEATURE_1_AND, BTI_FLAG|PAC_FLAG) > > #define END(name) \ > .cfi_endproc; \ > - .size name, .-name > + SIZE_PO(name) > diff --git a/libgcc/config/aarch64/crti.S b/libgcc/config/aarch64/crti.S > index 1371967c196..ed87a2ad696 100644 > --- a/libgcc/config/aarch64/crti.S > +++ b/libgcc/config/aarch64/crti.S > @@ -21,6 +21,8 @@ > # see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > # . > > +#include "aarch64-asm.h" > + > /* An executable stack is *not* required for these functions. */ > #if defined(__ELF__) && defined(__linux__) > .section .note.GNU-stack,"",%progbits > @@ -31,12 +33,6 @@ > # .init sections. Users may put any desired instructions in those > # sections. > > -#ifdef __ELF__ > -#define TYPE(x) .type x,function > -#else > -#define TYPE(x) > -#endif > - > # Note - this macro is complemented by the FUNC_END macro > # in crtn.S. If you change this macro you must also change > # that macro match. > @@ -53,7 +49,7 @@ > .section ".init" > .align 2 > .global _init > - TYPE(_init) > + TYPE_PO(_init) > _init: > FUNC_START > > @@ -61,7 +57,7 @@ _init: > .section ".fini" > .align 2 > .global _fini > - TYPE(_fini) > + TYPE_PO(_fini) > _fini: > FUNC_START > > diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S > index 671a86cfb87..af55ef88098 100644 > --- a/libgcc/config/aarch64/lse.S > +++ b/libgcc/config/aarch64/lse.S > @@ -51,6 +51,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > * indirectly, they do not need to start with a BTI instruction. > */ > > +#include "aarch64-asm.h" > #include "auto-target.h" > > /* Tell the assembler to accept LSE instructions. */ > @@ -61,7 +62,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > #endif > > /* Declare the symbol gating the LSE implementations. */ > - .hidden __aarch64_have_lse_atomics > + HIDDEN_PO(__aarch64_have_lse_atomics) > > /* Turn size and memory model defines into mnemonic fragments. */ > #if SIZE == 1 > @@ -171,15 +172,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > .text > .balign 16 > .globl \name > - .hidden \name > - .type \name, %function > + HIDDEN_PO(\name) > + TYPE_PO(\name) > .cfi_startproc > \name: > .endm > > .macro ENDFN name > .cfi_endproc > - .size \name, . - \name > + SIZE_PO(\name) > .endm > > /* Branch to LABEL if LSE is disabled. */