From: Richard Sandiford <richard.sandiford@arm.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 13/13] aarch64: Add costs for LD[34] and ST[34] postincrements
Date: Fri, 26 Mar 2021 16:18:48 +0000 [thread overview]
Message-ID: <mptsg4hq45z.fsf@arm.com> (raw)
In-Reply-To: <mptpmzlsxl1.fsf@arm.com> (Richard Sandiford's message of "Fri, 26 Mar 2021 16:12:42 +0000")
Most postincrements are cheap on Neoverse V1, but it's
generally better to avoid them on LD[34] and ST[34] instructions.
This patch adds separate address costs fields for these cases.
Other CPUs continue to use the same costs for all postincrements.
gcc/
* config/aarch64/aarch64-protos.h
(cpu_addrcost_table::post_modify_ld3_st3): New member variable.
(cpu_addrcost_table::post_modify_ld4_st4): Likewise.
* config/aarch64/aarch64.c (generic_addrcost_table): Update
accordingly, using the same costs as for post_modify.
(exynosm1_addrcost_table, xgene1_addrcost_table): Likewise.
(thunderx2t99_addrcost_table, thunderx3t110_addrcost_table):
(tsv110_addrcost_table, qdf24xx_addrcost_table): Likewise.
(a64fx_addrcost_table): Likewise.
(neoversev1_addrcost_table): New.
(neoversev1_tunings): Use neoversev1_addrcost_table.
(aarch64_address_cost): Use the new post_modify costs for CImode
and XImode.
---
gcc/config/aarch64/aarch64-protos.h | 2 ++
gcc/config/aarch64/aarch64.c | 45 +++++++++++++++++++++++++++--
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index ca1ed9e8758..d5d5417370e 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -177,6 +177,8 @@ struct cpu_addrcost_table
const struct scale_addr_mode_cost addr_scale_costs;
const int pre_modify;
const int post_modify;
+ const int post_modify_ld3_st3;
+ const int post_modify_ld4_st4;
const int register_offset;
const int register_sextend;
const int register_zextend;
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 6d961bea5dc..a573850b3fd 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -364,6 +364,8 @@ static const struct cpu_addrcost_table generic_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
0, /* register_offset */
0, /* register_sextend */
0, /* register_zextend */
@@ -380,6 +382,8 @@ static const struct cpu_addrcost_table exynosm1_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
1, /* register_offset */
1, /* register_sextend */
2, /* register_zextend */
@@ -396,6 +400,8 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
},
1, /* pre_modify */
1, /* post_modify */
+ 1, /* post_modify_ld3_st3 */
+ 1, /* post_modify_ld4_st4 */
0, /* register_offset */
1, /* register_sextend */
1, /* register_zextend */
@@ -412,6 +418,8 @@ static const struct cpu_addrcost_table thunderx2t99_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
2, /* register_offset */
3, /* register_sextend */
3, /* register_zextend */
@@ -428,6 +436,8 @@ static const struct cpu_addrcost_table thunderx3t110_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
2, /* register_offset */
3, /* register_sextend */
3, /* register_zextend */
@@ -444,6 +454,8 @@ static const struct cpu_addrcost_table tsv110_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
0, /* register_offset */
1, /* register_sextend */
1, /* register_zextend */
@@ -460,6 +472,8 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table =
},
1, /* pre_modify */
1, /* post_modify */
+ 1, /* post_modify_ld3_st3 */
+ 1, /* post_modify_ld4_st4 */
3, /* register_offset */
3, /* register_sextend */
3, /* register_zextend */
@@ -476,12 +490,32 @@ static const struct cpu_addrcost_table a64fx_addrcost_table =
},
0, /* pre_modify */
0, /* post_modify */
+ 0, /* post_modify_ld3_st3 */
+ 0, /* post_modify_ld4_st4 */
2, /* register_offset */
3, /* register_sextend */
3, /* register_zextend */
0, /* imm_offset */
};
+static const struct cpu_addrcost_table neoversev1_addrcost_table =
+{
+ {
+ 1, /* hi */
+ 0, /* si */
+ 0, /* di */
+ 1, /* ti */
+ },
+ 0, /* pre_modify */
+ 0, /* post_modify */
+ 3, /* post_modify_ld3_st3 */
+ 3, /* post_modify_ld4_st4 */
+ 0, /* register_offset */
+ 0, /* register_sextend */
+ 0, /* register_zextend */
+ 0 /* imm_offset */
+};
+
static const struct cpu_regmove_cost generic_regmove_cost =
{
1, /* GP2GP */
@@ -1777,7 +1811,7 @@ static const struct cpu_vector_cost neoversev1_vector_cost =
static const struct tune_params neoversev1_tunings =
{
&cortexa76_extra_costs,
- &generic_addrcost_table,
+ &neoversev1_addrcost_table,
&generic_regmove_cost,
&neoversev1_vector_cost,
&generic_branch_cost,
@@ -12077,7 +12111,14 @@ aarch64_address_cost (rtx x,
if (c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY)
cost += addr_cost->pre_modify;
else if (c == POST_INC || c == POST_DEC || c == POST_MODIFY)
- cost += addr_cost->post_modify;
+ {
+ if (mode == CImode)
+ cost += addr_cost->post_modify_ld3_st3;
+ else if (mode == XImode)
+ cost += addr_cost->post_modify_ld4_st4;
+ else
+ cost += addr_cost->post_modify;
+ }
else
gcc_unreachable ();
--
2.17.1
prev parent reply other threads:[~2021-03-26 16:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 16:12 aarch64: Opt-in tweaks to the AArch64 vector cost model Richard Sandiford
2021-03-26 16:14 ` [PATCH 01/13] aarch64: Add reduction costs to simd_vec_costs Richard Sandiford
2021-03-26 16:14 ` [PATCH 02/13] aarch64: Add vector costs for SVE CLAST[AB] and FADDA Richard Sandiford
2021-03-26 16:15 ` [PATCH 03/13] aarch64: Add costs for LD[234]/ST[234] permutes Richard Sandiford
2021-03-26 16:15 ` [PATCH 04/13] aarch64: Add costs for storing one element of a vector Richard Sandiford
2021-03-26 16:15 ` [PATCH 05/13] aarch64: Add costs for one element of a scatter store Richard Sandiford
2021-03-26 16:16 ` [PATCH 06/13] aarch64: Add a CPU-specific cost table for Neoverse V1 Richard Sandiford
2021-03-26 16:16 ` [PATCH 07/13] aarch64: Use an aarch64-specific structure for vector costing Richard Sandiford
2021-03-26 16:16 ` [PATCH 08/13] aarch64: Try to detect when Advanced SIMD code would be completely unrolled Richard Sandiford
2021-03-26 16:17 ` [PATCH 09/13] aarch64: Detect scalar extending loads Richard Sandiford
2021-03-26 16:17 ` [PATCH 10/13] aarch64: Cost comparisons embedded in COND_EXPRs Richard Sandiford
2021-03-26 16:18 ` [PATCH 11/13] aarch64: Ignore inductions when costing vector code Richard Sandiford
2021-03-26 16:18 ` [PATCH 12/13] aarch64: Take issue rate into account for vector loop costs Richard Sandiford
2021-03-26 16:18 ` Richard Sandiford [this message]
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