From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 1A6C23858D28 for ; Mon, 17 Jul 2023 14:44:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1A6C23858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F05F9C15; Mon, 17 Jul 2023 07:44:52 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2BD493F738; Mon, 17 Jul 2023 07:44:09 -0700 (PDT) From: Richard Sandiford To: juzhe.zhong@rivai.ai Mail-Followup-To: juzhe.zhong@rivai.ai,gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup References: <20230717144209.316540-1-juzhe.zhong@rivai.ai> Date: Mon, 17 Jul 2023 15:44:07 +0100 In-Reply-To: <20230717144209.316540-1-juzhe.zhong@rivai.ai> (juzhe zhong's message of "Mon, 17 Jul 2023 22:42:09 +0800") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-26.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: juzhe.zhong@rivai.ai writes: > From: Ju-Zhe Zhong > > Hi, Richard. > > RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc) > There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc) > > When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE: > rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186 > 13 | } > | ^ > 0xf7a5b1 partial_subreg_p(machine_mode, machine_mode) > ../../../riscv-gcc/gcc/rtl.h:3186 > 0x1407616 wider_subreg_mode(machine_mode, machine_mode) > ../../../riscv-gcc/gcc/rtl.h:3252 > 0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode) > ../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677 > 0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*) > ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146 > 0x2a2c142 rtl_ssa::function_info::simplify_phis() > ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258 > 0x2a2b3f0 rtl_ssa::function_info::function_info(function*) > ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51 > 0x1cebab9 pass_vsetvl::init() > ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578 > 0x1cec150 pass_vsetvl::execute(function*) > ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716 > > The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97] > When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () = V32QImode. > But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes). > Then combine_modes report ICE. > > gcc/ChangeLog: > > * rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred. OK if it passes testing. Thanks, Richard > --- > gcc/rtl-ssa/internals.inl | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/gcc/rtl-ssa/internals.inl b/gcc/rtl-ssa/internals.inl > index 0a61811289d..e49297c12b3 100644 > --- a/gcc/rtl-ssa/internals.inl > +++ b/gcc/rtl-ssa/internals.inl > @@ -673,6 +673,9 @@ combine_modes (machine_mode mode1, machine_mode mode2) > if (mode2 == E_BLKmode) > return mode1; > > + if (!ordered_p (GET_MODE_SIZE (mode1), GET_MODE_SIZE (mode2))) > + return BLKmode; > + > return wider_subreg_mode (mode1, mode2); > }