From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 103D3385E823 for ; Wed, 16 Jun 2021 12:28:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 103D3385E823 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94594113E; Wed, 16 Jun 2021 05:28:14 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 049B43F719; Wed, 16 Jun 2021 05:28:13 -0700 (PDT) From: Richard Sandiford To: Jonathan Wright Mail-Followup-To: Jonathan Wright , "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , Kyrylo Tkachov Subject: Re: [PATCH V2] aarch64: Model zero-high-half semantics of XTN instruction in RTL References: Date: Wed, 16 Jun 2021 13:28:12 +0100 In-Reply-To: (Jonathan Wright's message of "Wed, 16 Jun 2021 10:04:57 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2021 12:28:17 -0000 Jonathan Wright writes: > Hi, > > Version 2 of this patch adds tests to verify the benefit of this change. > > Ok for master? > > Thanks, > Jonathan > > --- > > gcc/ChangeLog: > > 2021-06-11 Jonathan Wright > > * config/aarch64/aarch64-simd.md (aarch64_xtn_insn_le): > Define - modeling zero-high-half semantics. > (aarch64_xtn): Change to an expander that emits the > appropriate instruction depending on endianness. > (aarch64_xtn_insn_be): Define - modeling zero-high-half > semantics. > (aarch64_xtn2_le): Rename to... > (aarch64_xtn2_insn_le): This. > (aarch64_xtn2_be): Rename to... > (aarch64_xtn2_insn_be): This. > (vec_pack_trunc_): Emit truncation instruction instead > of aarch64_xtn. > * config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode > attribute iterator. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests. OK, thanks. > From: Gcc-patches on behalf of Jonathan Wright via Gcc-patches > Sent: 15 June 2021 10:45 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH] aarch64: Model zero-high-half semantics of XTN instruction in RTL > > Hi, > > Modeling the zero-high-half semantics of the XTN narrowing > instruction in RTL indicates to the compiler that this is a totally > destructive operation. This enables more RTL simplifications and also > prevents some register allocation issues. > > Regression tested and bootstrapped on aarch64-none-linux-gnu - no > issues. > > Ok for master? > > Thanks, > Jonathan > > --- > > gcc/ChangeLog: > > 2021-06-11 Jonathan Wright > > * config/aarch64/aarch64-simd.md (aarch64_xtn_insn_le): > Define - modeling zero-high-half semantics. > (aarch64_xtn): Change to an expander that emits the > appropriate instruction depending on endianness. > (aarch64_xtn_insn_be): Define - modeling zero-high-half > semantics. > (aarch64_xtn2_le): Rename to... > (aarch64_xtn2_insn_le): This. > (aarch64_xtn2_be): Rename to... > (aarch64_xtn2_insn_be): This. > (vec_pack_trunc_): Emit truncation instruction instead > of aarch64_xtn. > * config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode > attribute iterator. > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index e750faed1dbd940cdfa216d858b98f3bc25bba42..b23556b551cbbef420950007e9714acf190a534d 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1690,17 +1690,48 @@ > > ;; Narrowing operations. > > -;; For doubles. > +(define_insn "aarch64_xtn_insn_le" > + [(set (match_operand: 0 "register_operand" "=w") > + (vec_concat: > + (truncate: (match_operand:VQN 1 "register_operand" "w")) > + (match_operand: 2 "aarch64_simd_or_scalar_imm_zero")))] > + "TARGET_SIMD && !BYTES_BIG_ENDIAN" > + "xtn\\t%0., %1." > + [(set_attr "type" "neon_move_narrow_q")] > +) > > -(define_insn "aarch64_xtn" > - [(set (match_operand: 0 "register_operand" "=w") > - (truncate: (match_operand:VQN 1 "register_operand" "w")))] > - "TARGET_SIMD" > +(define_insn "aarch64_xtn_insn_be" > + [(set (match_operand: 0 "register_operand" "=w") > + (vec_concat: > + (match_operand: 2 "aarch64_simd_or_scalar_imm_zero") > + (truncate: (match_operand:VQN 1 "register_operand" "w"))))] > + "TARGET_SIMD && BYTES_BIG_ENDIAN" > "xtn\\t%0., %1." > [(set_attr "type" "neon_move_narrow_q")] > ) > > -(define_insn "aarch64_xtn2_le" > +(define_expand "aarch64_xtn" > + [(set (match_operand: 0 "register_operand") > + (truncate: (match_operand:VQN 1 "register_operand")))] > + "TARGET_SIMD" > + { > + rtx tmp = gen_reg_rtx (mode); > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_aarch64_xtn_insn_be (tmp, operands[1], > + CONST0_RTX (mode))); > + else > + emit_insn (gen_aarch64_xtn_insn_le (tmp, operands[1], > + CONST0_RTX (mode))); > + > + /* The intrinsic expects a narrow result, so emit a subreg that will get > + optimized away as appropriate. */ > + emit_move_insn (operands[0], lowpart_subreg (mode, tmp, > + mode)); > + DONE; > + } > +) > + > +(define_insn "aarch64_xtn2_insn_le" > [(set (match_operand: 0 "register_operand" "=w") > (vec_concat: > (match_operand: 1 "register_operand" "0") > @@ -1710,7 +1741,7 @@ > [(set_attr "type" "neon_move_narrow_q")] > ) > > -(define_insn "aarch64_xtn2_be" > +(define_insn "aarch64_xtn2_insn_be" > [(set (match_operand: 0 "register_operand" "=w") > (vec_concat: > (truncate: (match_operand:VQN 2 "register_operand" "w")) > @@ -1727,15 +1758,17 @@ > "TARGET_SIMD" > { > if (BYTES_BIG_ENDIAN) > - emit_insn (gen_aarch64_xtn2_be (operands[0], operands[1], > - operands[2])); > + emit_insn (gen_aarch64_xtn2_insn_be (operands[0], operands[1], > + operands[2])); > else > - emit_insn (gen_aarch64_xtn2_le (operands[0], operands[1], > - operands[2])); > + emit_insn (gen_aarch64_xtn2_insn_le (operands[0], operands[1], > + operands[2])); > DONE; > } > ) > > +;; Packing doubles. > + > (define_expand "vec_pack_trunc_" > [(match_operand: 0 "register_operand") > (match_operand:VDN 1 "register_operand") > @@ -1748,10 +1781,35 @@ > > emit_insn (gen_move_lo_quad_ (tempreg, operands[lo])); > emit_insn (gen_move_hi_quad_ (tempreg, operands[hi])); > - emit_insn (gen_aarch64_xtn (operands[0], tempreg)); > + emit_insn (gen_trunc2 (operands[0], tempreg)); > DONE; > }) > > +;; Packing quads. > + > +(define_expand "vec_pack_trunc_" > + [(set (match_operand: 0 "register_operand") > + (vec_concat: > + (truncate: (match_operand:VQN 1 "register_operand")) > + (truncate: (match_operand:VQN 2 "register_operand"))))] > + "TARGET_SIMD" > + { > + rtx tmpreg = gen_reg_rtx (mode); > + int lo = BYTES_BIG_ENDIAN ? 2 : 1; > + int hi = BYTES_BIG_ENDIAN ? 1 : 2; > + > + emit_insn (gen_trunc2 (tmpreg, operands[lo])); > + > + if (BYTES_BIG_ENDIAN) > + emit_insn (gen_aarch64_xtn2_insn_be (operands[0], tmpreg, > + operands[hi])); > + else > + emit_insn (gen_aarch64_xtn2_insn_le (operands[0], tmpreg, > + operands[hi])); > + DONE; > + } > +) > + > (define_insn "aarch64_shrn_insn_le" > [(set (match_operand: 0 "register_operand" "=w") > (vec_concat: > @@ -1936,29 +1994,6 @@ > } > ) > > -;; For quads. > - > -(define_expand "vec_pack_trunc_" > - [(set (match_operand: 0 "register_operand") > - (vec_concat: > - (truncate: (match_operand:VQN 1 "register_operand")) > - (truncate: (match_operand:VQN 2 "register_operand"))))] > - "TARGET_SIMD" > - { > - rtx tmpreg = gen_reg_rtx (mode); > - int lo = BYTES_BIG_ENDIAN ? 2 : 1; > - int hi = BYTES_BIG_ENDIAN ? 1 : 2; > - > - emit_insn (gen_aarch64_xtn (tmpreg, operands[lo])); > - > - if (BYTES_BIG_ENDIAN) > - emit_insn (gen_aarch64_xtn2_be (operands[0], tmpreg, operands[hi])); > - else > - emit_insn (gen_aarch64_xtn2_le (operands[0], tmpreg, operands[hi])); > - DONE; > - } > -) > - > ;; Widening operations. > > (define_insn "aarch64_simd_vec_unpack_lo_" > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index e9047d00d979411752d9aeddaadb05ec38e3a145..caa42f8f169fbf2cf46a90cf73dee05619acc300 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -1257,6 +1257,8 @@ > ;; Narrowed modes for VDN. > (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") > (DI "V2SI")]) > +(define_mode_attr Vnarrowd [(V4HI "v8qi") (V2SI "v4hi") > + (DI "v2si")]) > > ;; Narrowed double-modes for VQN (Used for XTN). > (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") > diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c > index 27fa0e640ab2b37781376c40ce4ca37602c72393..78c474f3025cbf56d14323d8f05bfb73e003ebfd 100644 > --- a/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c > +++ b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c > @@ -48,6 +48,21 @@ TEST_SHIFT (vqrshrun_n, uint8x16_t, int16x8_t, s16, u8) > TEST_SHIFT (vqrshrun_n, uint16x8_t, int32x4_t, s32, u16) > TEST_SHIFT (vqrshrun_n, uint32x4_t, int64x2_t, s64, u32) > > +#define TEST_UNARY(name, rettype, intype, fs, rs) \ > + rettype test_ ## name ## _ ## fs ## _zero_high \ > + (intype a) \ > + { \ > + return vcombine_ ## rs (name ## _ ## fs (a), \ > + vdup_n_ ## rs (0)); \ > + } > + > +TEST_UNARY (vmovn, int8x16_t, int16x8_t, s16, s8) > +TEST_UNARY (vmovn, int16x8_t, int32x4_t, s32, s16) > +TEST_UNARY (vmovn, int32x4_t, int64x2_t, s64, s32) > +TEST_UNARY (vmovn, uint8x16_t, uint16x8_t, u16, u8) > +TEST_UNARY (vmovn, uint16x8_t, uint32x4_t, u32, u16) > +TEST_UNARY (vmovn, uint32x4_t, uint64x2_t, u64, u32) > + > /* { dg-final { scan-assembler-not "dup\\t" } } */ > > /* { dg-final { scan-assembler-times "\\trshrn\\tv" 6} } */ > @@ -58,3 +73,4 @@ TEST_SHIFT (vqrshrun_n, uint32x4_t, int64x2_t, s64, u32) > /* { dg-final { scan-assembler-times "\\tuqshrn\\tv" 3} } */ > /* { dg-final { scan-assembler-times "\\tsqrshrn\\tv" 3} } */ > /* { dg-final { scan-assembler-times "\\tuqrshrn\\tv" 3} } */ > +/* { dg-final { scan-assembler-times "\\txtn\\tv" 6} } */