From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 88C7A3858D28 for ; Tue, 11 Apr 2023 11:11:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 88C7A3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 878A7D75; Tue, 11 Apr 2023 04:12:22 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20D2B3F6C4; Tue, 11 Apr 2023 04:11:37 -0700 (PDT) From: Richard Sandiford To: Richard Biener Mail-Followup-To: Richard Biener ,juzhe.zhong@rivai.ai, Jeff Law , gcc-patches , "kito.cheng" , palmer , jakub , richard.sandiford@arm.com Cc: juzhe.zhong@rivai.ai, Jeff Law , gcc-patches , "kito.cheng" , palmer , jakub Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit References: <20230410144808.324346-1-juzhe.zhong@rivai.ai> <89f088ec-8692-01f5-0395-5a66ddf085d7@gmail.com> <47D962C7C724E3A2+20230410231445834316202@rivai.ai> Date: Tue, 11 Apr 2023 12:11:35 +0100 In-Reply-To: (Richard Biener's message of "Tue, 11 Apr 2023 10:59:30 +0000 (UTC)") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-25.2 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Richard Biener writes: > On Tue, 11 Apr 2023, Richard Sandiford wrote: > >> writes: >> > ARM SVE has?svint8_t, svint8x2_t, svint8x3_t, svint8x4_t >> > As far as I known, they don't have tuple type for partial vector. >> >> Yeah, there are no separate types for partial vectors, but there >> are separate modes. E.g. VNx2QI is a partial vector of QIs, >> with each QI stored in a 64-bit container. >> >> I agree with all the comments about the danger of growing the number of >> modes too much. But it looks like rtx_def should be easy to rearrange. >> Unless I'm missing something, there are less than 256 rtx codes at >> present. So one simple option would be to make the code 8 bits and >> the machine_mode 16 bits (and swap them, so that they stay well-aligned >> wrt their size). > > But then the bigger issue is tree_type_common where we agreed to > bump precision from 10 to 16 bits, with bumping machine_mode from > 8 to 16 we then are left with only 3 spare bits from 15 now - if > the comments are correct. Hmm, true. I guess the two options are: (1) Increase the size of the machine_mode field by the smallest amount possible (accepting that it will be non-power-of-2). I'd be surprised if that's a significant performance issue, since modes aren't as fundamental to trees as rtxes (and since a non-power-of-2 precision doesn't seem to have hurt). (2) Increase the size to 16 anyway, with the understanding that the mode is the first thing to shrink if we need a fourth spare bit. > In tree_decl_common we have 13 unused bits. > > IRA allocno would also increase and it's hard_regno field looks > suspiciously unaligned already (unless unsigned/signed re-aligns > bitfields). Yeah, agree it looks unaligned. If I've read it correctly, it looks like there's a 32-bit gap on 64-bit hosts before objects[2]. So perhaps we could move the mode fields there and put hard_regno where the modes are now. Thanks, Richard