From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B8BE1385828B for ; Fri, 23 Sep 2022 10:03:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B8BE1385828B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1ADC139F; Fri, 23 Sep 2022 03:03:59 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5731A3F73D; Fri, 23 Sep 2022 03:03:52 -0700 (PDT) From: Richard Sandiford To: Tamar Christina Mail-Followup-To: Tamar Christina ,"gcc-patches\@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov , richard.sandiford@arm.com Cc: "gcc-patches\@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov Subject: Re: [PATCH 2/2]AArch64 Add support for neg on v1df References: Date: Fri, 23 Sep 2022 11:03:51 +0100 In-Reply-To: (Tamar Christina's message of "Fri, 23 Sep 2022 09:43:02 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-47.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tamar Christina writes: >> -----Original Message----- >> From: Richard Sandiford >> Sent: Friday, September 23, 2022 5:30 AM >> To: Tamar Christina >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw >> ; Marcus Shawcroft >> ; Kyrylo Tkachov >> Subject: Re: [PATCH 2/2]AArch64 Add support for neg on v1df >> >> Tamar Christina writes: >> > Hi All, >> > >> > This adds support for using scalar fneg on the V1DF type. >> > >> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. >> > >> > Ok for master? >> >> Why just this one operation though? Couldn't we extend iterators like >> GPF_F16 to include V1DF, avoiding the need for new patterns? >> > > Simply because it's the only one I know how to generate code for. > I can change GPF_F16 but I don't know under which circumstances we'd generate > a V1DF for the other operations. We'd do it for things like: __Float64x1_t foo (__Float64x1_t x) { return -x; } if the pattern is available, instead of using subregs. So one way would be to scan the expand rtl dump for subregs. If the point is that there is no observable difference between defining 1-element vector ops and not, except for this one case, then that suggests we should handle this case in target-independent code instead. There's no point forcing every target that has V1DF to define a duplicate of the DF neg pattern. Thanks, Richard > > So if it's ok to do so without full test coverage I'm happy to do so... > > Tamar. > >> Richard >> >> > >> > Thanks, >> > Tamar >> > >> > gcc/ChangeLog: >> > >> > * config/aarch64/aarch64-simd.md (negv1df2): New. >> > >> > gcc/testsuite/ChangeLog: >> > >> > * gcc.target/aarch64/simd/addsub_2.c: New test. >> > >> > --- inline copy of patch -- >> > diff --git a/gcc/config/aarch64/aarch64-simd.md >> > b/gcc/config/aarch64/aarch64-simd.md >> > index >> > >> f4152160084d6b6f34bd69f0ba6386c1ab50f77e..cf8c094bd4b76981cef2dd5dd7 >> b8 >> > e6be0d56101f 100644 >> > --- a/gcc/config/aarch64/aarch64-simd.md >> > +++ b/gcc/config/aarch64/aarch64-simd.md >> > @@ -2713,6 +2713,14 @@ (define_insn "neg2" >> > [(set_attr "type" "neon_fp_neg_")] >> > ) >> > >> > +(define_insn "negv1df2" >> > + [(set (match_operand:V1DF 0 "register_operand" "=w") >> > + (neg:V1DF (match_operand:V1DF 1 "register_operand" "w")))] >> > +"TARGET_SIMD" >> > + "fneg\\t%d0, %d1" >> > + [(set_attr "type" "neon_fp_neg_d")] >> > +) >> > + >> > (define_insn "abs2" >> > [(set (match_operand:VHSDF 0 "register_operand" "=w") >> > (abs:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))] >> > diff --git a/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> > b/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> > new file mode 100644 >> > index >> > >> 0000000000000000000000000000000000000000..55a7365e897f8af509de953129 >> e0 >> > f516974f7ca8 >> > --- /dev/null >> > +++ b/gcc/testsuite/gcc.target/aarch64/simd/addsub_2.c >> > @@ -0,0 +1,22 @@ >> > +/* { dg-do compile } */ >> > +/* { dg-options "-Ofast" } */ >> > +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } >> > +} */ >> > + >> > +#pragma GCC target "+nosve" >> > + >> > +/* >> > +** f1: >> > +** ... >> > +** fneg d[0-9]+, d[0-9]+ >> > +** fadd v[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s >> > +** ... >> > +*/ >> > +void f1 (float *restrict a, float *restrict b, float *res, int n) { >> > + for (int i = 0; i < 2; i+=2) >> > + { >> > + res[i+0] = a[i+0] + b[i+0]; >> > + res[i+1] = a[i+1] - b[i+1]; >> > + } >> > +} >> > +