* [PATCH] aarch64: Use type-qualified builtins for [R]SHRN[2] Neon intrinsics
@ 2021-11-11 10:14 Jonathan Wright
2021-11-11 10:20 ` Richard Sandiford
0 siblings, 1 reply; 2+ messages in thread
From: Jonathan Wright @ 2021-11-11 10:14 UTC (permalink / raw)
To: gcc-patches; +Cc: Richard Sandiford, Kyrylo Tkachov
[-- Attachment #1: Type: text/plain, Size: 880 bytes --]
Hi,
Thus patch declares unsigned type-qualified builtins and uses them for
[R]SHRN[2] Neon intrinsics. This removes the need for casts in
arm_neon.h.
Bootstrapped and regression tested on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-11-08 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Declare type-
qualified builtins for [R]SHRN[2].
* config/aarch64/arm_neon.h (vshrn_n_u16): Use type-qualified
builtin and remove casts.
(vshrn_n_u32): Likewise.
(vshrn_n_u64): Likewise.
(vrshrn_high_n_u16): Likewise.
(vrshrn_high_n_u32): Likewise.
(vrshrn_high_n_u64): Likewise.
(vrshrn_n_u16): Likewise.
(vrshrn_n_u32): Likewise.
(vrshrn_n_u64): Likewise.
(vshrn_high_n_u16): Likewise.
(vshrn_high_n_u32): Likewise.
(vshrn_high_n_u64): Likewise.
[-- Attachment #2: rb15032.patch --]
[-- Type: application/octet-stream, Size: 5360 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 5e6df6abe3f5b42710a266d0b2a7a1e4597975a6..46ec2f9bfc509e5e460334d4c5324ddf18703639 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -253,15 +253,19 @@
/* Implemented by aarch64_shrn<mode>". */
BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE)
+ BUILTIN_VQN (USHIFTIMM, shrn, 0, NONE)
/* Implemented by aarch64_shrn2<mode>. */
- BUILTIN_VQN (SHIFTACC, shrn2, 0, NONE)
+ BUILTIN_VQN (SHIFT2IMM, shrn2, 0, NONE)
+ BUILTIN_VQN (USHIFT2IMM, shrn2, 0, NONE)
/* Implemented by aarch64_rshrn<mode>". */
BUILTIN_VQN (SHIFTIMM, rshrn, 0, NONE)
+ BUILTIN_VQN (USHIFTIMM, rshrn, 0, NONE)
/* Implemented by aarch64_rshrn2<mode>. */
- BUILTIN_VQN (SHIFTACC, rshrn2, 0, NONE)
+ BUILTIN_VQN (SHIFT2IMM, rshrn2, 0, NONE)
+ BUILTIN_VQN (USHIFT2IMM, rshrn2, 0, NONE)
/* Implemented by aarch64_<su>mlsl<mode>. */
BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 51cedab19d8d1c261fbcf9a6d3202c2e1b513183..37f02e2a24fbc85f23ea73e2fd0e06deac7db87e 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -7606,21 +7606,21 @@ __extension__ extern __inline uint8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_n_u16 (uint16x8_t __a, const int __b)
{
- return (uint8x8_t)__builtin_aarch64_shrnv8hi ((int16x8_t)__a, __b);
+ return __builtin_aarch64_shrnv8hi_uus (__a, __b);
}
__extension__ extern __inline uint16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_n_u32 (uint32x4_t __a, const int __b)
{
- return (uint16x4_t)__builtin_aarch64_shrnv4si ((int32x4_t)__a, __b);
+ return __builtin_aarch64_shrnv4si_uus (__a, __b);
}
__extension__ extern __inline uint32x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_n_u64 (uint64x2_t __a, const int __b)
{
- return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b);
+ return __builtin_aarch64_shrnv2di_uus (__a, __b);
}
__extension__ extern __inline int32x4_t
@@ -8387,24 +8387,21 @@ __extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c)
{
- return (uint8x16_t) __builtin_aarch64_rshrn2v8hi ((int8x8_t) __a,
- (int16x8_t) __b, __c);
+ return __builtin_aarch64_rshrn2v8hi_uuus (__a, __b, __c);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c)
{
- return (uint16x8_t) __builtin_aarch64_rshrn2v4si ((int16x4_t) __a,
- (int32x4_t) __b, __c);
+ return __builtin_aarch64_rshrn2v4si_uuus (__a, __b, __c);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c)
{
- return (uint32x4_t) __builtin_aarch64_rshrn2v2di ((int32x2_t)__a,
- (int64x2_t)__b, __c);
+ return __builtin_aarch64_rshrn2v2di_uuus (__a, __b, __c);
}
__extension__ extern __inline int8x8_t
@@ -8432,21 +8429,21 @@ __extension__ extern __inline uint8x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_n_u16 (uint16x8_t __a, const int __b)
{
- return (uint8x8_t) __builtin_aarch64_rshrnv8hi ((int16x8_t) __a, __b);
+ return __builtin_aarch64_rshrnv8hi_uus (__a, __b);
}
__extension__ extern __inline uint16x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_n_u32 (uint32x4_t __a, const int __b)
{
- return (uint16x4_t) __builtin_aarch64_rshrnv4si ((int32x4_t) __a, __b);
+ return __builtin_aarch64_rshrnv4si_uus (__a, __b);
}
__extension__ extern __inline uint32x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vrshrn_n_u64 (uint64x2_t __a, const int __b)
{
- return (uint32x2_t) __builtin_aarch64_rshrnv2di ((int64x2_t) __a, __b);
+ return __builtin_aarch64_rshrnv2di_uus (__a, __b);
}
__extension__ extern __inline uint32x2_t
@@ -8488,24 +8485,21 @@ __extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c)
{
- return (uint8x16_t)
- __builtin_aarch64_shrn2v8hi ((int8x8_t) __a, (int16x8_t) __b, __c);
+ return __builtin_aarch64_shrn2v8hi_uuus (__a, __b, __c);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c)
{
- return (uint16x8_t)
- __builtin_aarch64_shrn2v4si ((int16x4_t) __a, (int32x4_t) __b, __c);
+ return __builtin_aarch64_shrn2v4si_uuus (__a, __b, __c);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c)
{
- return (uint32x4_t)
- __builtin_aarch64_shrn2v2di ((int32x2_t) __a, (int64x2_t) __b, __c);
+ return __builtin_aarch64_shrn2v2di_uuus (__a, __b, __c);
}
__extension__ extern __inline poly8x8_t
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] aarch64: Use type-qualified builtins for [R]SHRN[2] Neon intrinsics
2021-11-11 10:14 [PATCH] aarch64: Use type-qualified builtins for [R]SHRN[2] Neon intrinsics Jonathan Wright
@ 2021-11-11 10:20 ` Richard Sandiford
0 siblings, 0 replies; 2+ messages in thread
From: Richard Sandiford @ 2021-11-11 10:20 UTC (permalink / raw)
To: Jonathan Wright; +Cc: gcc-patches, Kyrylo Tkachov
Jonathan Wright <Jonathan.Wright@arm.com> writes:
> Hi,
>
> Thus patch declares unsigned type-qualified builtins and uses them for
> [R]SHRN[2] Neon intrinsics. This removes the need for casts in
> arm_neon.h.
>
> Bootstrapped and regression tested on aarch64-none-linux-gnu - no
> issues.
>
> Ok for master?
>
> Thanks,
> Jonathan
>
> ---
>
> gcc/ChangeLog:
>
> 2021-11-08 Jonathan Wright <jonathan.wright@arm.com>
>
> * config/aarch64/aarch64-simd-builtins.def: Declare type-
> qualified builtins for [R]SHRN[2].
> * config/aarch64/arm_neon.h (vshrn_n_u16): Use type-qualified
> builtin and remove casts.
> (vshrn_n_u32): Likewise.
> (vshrn_n_u64): Likewise.
> (vrshrn_high_n_u16): Likewise.
> (vrshrn_high_n_u32): Likewise.
> (vrshrn_high_n_u64): Likewise.
> (vrshrn_n_u16): Likewise.
> (vrshrn_n_u32): Likewise.
> (vrshrn_n_u64): Likewise.
> (vshrn_high_n_u16): Likewise.
> (vshrn_high_n_u32): Likewise.
> (vshrn_high_n_u64): Likewise.
OK, thanks.
Richard
>
> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
> index 5e6df6abe3f5b42710a266d0b2a7a1e4597975a6..46ec2f9bfc509e5e460334d4c5324ddf18703639 100644
> --- a/gcc/config/aarch64/aarch64-simd-builtins.def
> +++ b/gcc/config/aarch64/aarch64-simd-builtins.def
> @@ -253,15 +253,19 @@
>
> /* Implemented by aarch64_shrn<mode>". */
> BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE)
> + BUILTIN_VQN (USHIFTIMM, shrn, 0, NONE)
>
> /* Implemented by aarch64_shrn2<mode>. */
> - BUILTIN_VQN (SHIFTACC, shrn2, 0, NONE)
> + BUILTIN_VQN (SHIFT2IMM, shrn2, 0, NONE)
> + BUILTIN_VQN (USHIFT2IMM, shrn2, 0, NONE)
>
> /* Implemented by aarch64_rshrn<mode>". */
> BUILTIN_VQN (SHIFTIMM, rshrn, 0, NONE)
> + BUILTIN_VQN (USHIFTIMM, rshrn, 0, NONE)
>
> /* Implemented by aarch64_rshrn2<mode>. */
> - BUILTIN_VQN (SHIFTACC, rshrn2, 0, NONE)
> + BUILTIN_VQN (SHIFT2IMM, rshrn2, 0, NONE)
> + BUILTIN_VQN (USHIFT2IMM, rshrn2, 0, NONE)
>
> /* Implemented by aarch64_<su>mlsl<mode>. */
> BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE)
> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
> index 51cedab19d8d1c261fbcf9a6d3202c2e1b513183..37f02e2a24fbc85f23ea73e2fd0e06deac7db87e 100644
> --- a/gcc/config/aarch64/arm_neon.h
> +++ b/gcc/config/aarch64/arm_neon.h
> @@ -7606,21 +7606,21 @@ __extension__ extern __inline uint8x8_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_n_u16 (uint16x8_t __a, const int __b)
> {
> - return (uint8x8_t)__builtin_aarch64_shrnv8hi ((int16x8_t)__a, __b);
> + return __builtin_aarch64_shrnv8hi_uus (__a, __b);
> }
>
> __extension__ extern __inline uint16x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_n_u32 (uint32x4_t __a, const int __b)
> {
> - return (uint16x4_t)__builtin_aarch64_shrnv4si ((int32x4_t)__a, __b);
> + return __builtin_aarch64_shrnv4si_uus (__a, __b);
> }
>
> __extension__ extern __inline uint32x2_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_n_u64 (uint64x2_t __a, const int __b)
> {
> - return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b);
> + return __builtin_aarch64_shrnv2di_uus (__a, __b);
> }
>
> __extension__ extern __inline int32x4_t
> @@ -8387,24 +8387,21 @@ __extension__ extern __inline uint8x16_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c)
> {
> - return (uint8x16_t) __builtin_aarch64_rshrn2v8hi ((int8x8_t) __a,
> - (int16x8_t) __b, __c);
> + return __builtin_aarch64_rshrn2v8hi_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline uint16x8_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c)
> {
> - return (uint16x8_t) __builtin_aarch64_rshrn2v4si ((int16x4_t) __a,
> - (int32x4_t) __b, __c);
> + return __builtin_aarch64_rshrn2v4si_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c)
> {
> - return (uint32x4_t) __builtin_aarch64_rshrn2v2di ((int32x2_t)__a,
> - (int64x2_t)__b, __c);
> + return __builtin_aarch64_rshrn2v2di_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline int8x8_t
> @@ -8432,21 +8429,21 @@ __extension__ extern __inline uint8x8_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_n_u16 (uint16x8_t __a, const int __b)
> {
> - return (uint8x8_t) __builtin_aarch64_rshrnv8hi ((int16x8_t) __a, __b);
> + return __builtin_aarch64_rshrnv8hi_uus (__a, __b);
> }
>
> __extension__ extern __inline uint16x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_n_u32 (uint32x4_t __a, const int __b)
> {
> - return (uint16x4_t) __builtin_aarch64_rshrnv4si ((int32x4_t) __a, __b);
> + return __builtin_aarch64_rshrnv4si_uus (__a, __b);
> }
>
> __extension__ extern __inline uint32x2_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vrshrn_n_u64 (uint64x2_t __a, const int __b)
> {
> - return (uint32x2_t) __builtin_aarch64_rshrnv2di ((int64x2_t) __a, __b);
> + return __builtin_aarch64_rshrnv2di_uus (__a, __b);
> }
>
> __extension__ extern __inline uint32x2_t
> @@ -8488,24 +8485,21 @@ __extension__ extern __inline uint8x16_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c)
> {
> - return (uint8x16_t)
> - __builtin_aarch64_shrn2v8hi ((int8x8_t) __a, (int16x8_t) __b, __c);
> + return __builtin_aarch64_shrn2v8hi_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline uint16x8_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c)
> {
> - return (uint16x8_t)
> - __builtin_aarch64_shrn2v4si ((int16x4_t) __a, (int32x4_t) __b, __c);
> + return __builtin_aarch64_shrn2v4si_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline uint32x4_t
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c)
> {
> - return (uint32x4_t)
> - __builtin_aarch64_shrn2v2di ((int32x2_t) __a, (int64x2_t) __b, __c);
> + return __builtin_aarch64_shrn2v2di_uuus (__a, __b, __c);
> }
>
> __extension__ extern __inline poly8x8_t
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2021-11-11 10:20 ` Richard Sandiford
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