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From: Richard Sandiford <richard.sandiford@arm.com>
To: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
	 Richard Earnshaw <Richard.Earnshaw@arm.com>
Subject: Re: [PATCH] AArch64: Fix printing of 2-instruction alternatives
Date: Mon, 20 May 2024 10:58:16 +0100	[thread overview]
Message-ID: <mptwmnoby9z.fsf@arm.com> (raw)
In-Reply-To: <PAWPR08MB8982150949151D8BD7A94FE183E52@PAWPR08MB8982.eurprd08.prod.outlook.com> (Wilco Dijkstra's message of "Wed, 15 May 2024 10:15:01 +0000")

Wilco Dijkstra <Wilco.Dijkstra@arm.com> writes:
> Add missing '\' in 2-instruction movsi/di alternatives so that they are
> printed on separate lines.
>
> Passes bootstrap and regress, OK for commit once stage 1 reopens?
>
> gcc:
>         * config/aarch64/aarch64.md (movsi_aarch64): Use '\;' to force
>         newline in 2-instruction pattern.
>         (movdi_aarch64): Likewise.

Oops, good catch.  Ok for trunk, thanks.

Richard

>
> ---
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 1a2e01284249223565cd12cf1bfd5db5475e56fb..5416c2e3b2002d04444e53baf23e7c0048ddf683 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -1447,7 +1447,7 @@ (define_insn_and_split "*movsi_aarch64"
>       [w  , m  ; load_4   , fp  , 4] ldr\t%s0, %1
>       [m  , r Z; store_4  , *   , 4] str\t%w1, %0
>       [m  , w  ; store_4  , fp  , 4] str\t%s1, %0
> -     [r  , Usw; load_4   , *   , 8] adrp\t%x0, %A1;ldr\t%w0, [%x0, %L1]
> +     [r  , Usw; load_4   , *   , 8] adrp\t%x0, %A1\;ldr\t%w0, [%x0, %L1]
>       [r  , Usa; adr      , *   , 4] adr\t%x0, %c1
>       [r  , Ush; adr      , *   , 4] adrp\t%x0, %A1
>       [w  , r Z; f_mcr    , fp  , 4] fmov\t%s0, %w1
> @@ -1484,7 +1484,7 @@ (define_insn_and_split "*movdi_aarch64"
>       [w, m  ; load_8   , fp  , 4] ldr\t%d0, %1
>       [m, r Z; store_8  , *   , 4] str\t%x1, %0
>       [m, w  ; store_8  , fp  , 4] str\t%d1, %0
> -     [r, Usw; load_8   , *   , 8] << TARGET_ILP32 ? "adrp\t%0, %A1;ldr\t%w0, [%0, %L1]" : "adrp\t%0, %A1;ldr\t%0, [%0, %L1]";
> +     [r, Usw; load_8   , *   , 8] << TARGET_ILP32 ? "adrp\t%0, %A1\;ldr\t%w0, [%0, %L1]" : "adrp\t%0, %A1\;ldr\t%0, [%0, %L1]";
>       [r, Usa; adr      , *   , 4] adr\t%x0, %c1
>       [r, Ush; adr      , *   , 4] adrp\t%x0, %A1
>       [w, r Z; f_mcr    , fp  , 4] fmov\t%d0, %x1

      reply	other threads:[~2024-05-20  9:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-15 10:15 Wilco Dijkstra
2024-05-20  9:58 ` Richard Sandiford [this message]

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