From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 45C6C3858D1E for ; Tue, 7 Nov 2023 23:18:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 45C6C3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 45C6C3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699399101; cv=none; b=H6w10l+ZZCLscd+OJEqBmHaXaIE4J15Khg0CKGjlAIfz+FbB3lqT66HoooyVDQHNh9fV2lyqUsWoXeM/e0Oxjrq4TbSQIiNda/uVSuk21KbNW4ewOnpga0vpkafRR3WZ4Cm0VU1IGM+2azWxXaN9/wxbPkqcdI0Klj8jU+g0b7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699399101; c=relaxed/simple; bh=J2ldPEDa/be732BtwVkgvWixKFfACI4Vb1ossczcmwQ=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=W+IheisRi1pk2/iuN/nbNHHl6IWr6jxw9cIFpcAIxcfhhZlZk0xb/pjUWNbCGVHiS0CUe8XcBDVJ8VDrcwSmc9O3gkqz1FSZoFdfKWfx2W3Cc8e0DSZe94c/+KXeR7L88WA2GLPiGMCKicMMLlQLaeiialYr9d4IRe6jyN4dtF8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A2591476; Tue, 7 Nov 2023 15:19:03 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 502BC3F64C; Tue, 7 Nov 2023 15:18:18 -0800 (PST) From: Richard Sandiford To: Victor Do Nascimento Mail-Followup-To: Victor Do Nascimento ,, , , richard.sandiford@arm.com Cc: , , Subject: Re: [PATCH 1/5] aarch64: Add march flags for +the and +d128 arch extensions References: <20231107103211.2837188-1-victor.donascimento@arm.com> <20231107103211.2837188-2-victor.donascimento@arm.com> Date: Tue, 07 Nov 2023 23:18:17 +0000 In-Reply-To: <20231107103211.2837188-2-victor.donascimento@arm.com> (Victor Do Nascimento's message of "Tue, 7 Nov 2023 10:30:10 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-23.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Victor Do Nascimento writes: > Given the introduction of optional 128-bit page table descriptor and > translation hardening extension support with the Arm9.4-a > architecture, this introduces the relevant flags to enable the reading > and writing of 128-bit system registers. > > The `+d128' -march modifier enables the use of the following ACLE > builtin functions: > > * __uint128_t __arm_rsr128(const char *special_register); > * void __arm_wsr128(const char *special_register, __uint128_t value); > > and defines the __ARM_FEATURE_SYSREG128 macro to 1. > > Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register > implementations are also reliant on the enablement of the `+the' flag, > which is thus also implemented in this patch. > > gcc/ChangeLog: > > * config/aarch64/aarch64-arches.def (armv8.9-a): New. > (armv9.4-a): Likewise. > * config/aarch64/aarch64-option-extensions.def (d128): Likewise. > (the): Likewise. > * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise. > (AARCH64_ISA_V8_9A): Likewise. > (TARGET_ARMV9_4): Likewise. > (AARCH64_ISA_D128): Likewise. > (AARCH64_ISA_THE): Likewise. > (TARGET_D128): Likewise. > * doc/invoke.texi (AArch64 Options): Document new -march flags > and extensions. OK, thanks. Richard > --- > gcc/config/aarch64/aarch64-arches.def | 2 ++ > gcc/config/aarch64/aarch64-c.cc | 1 + > gcc/config/aarch64/aarch64-option-extensions.def | 4 ++++ > gcc/config/aarch64/aarch64.h | 15 +++++++++++++++ > gcc/doc/invoke.texi | 6 ++++++ > 5 files changed, 28 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def > index 7ae92aa8e98..becccb801d0 100644 > --- a/gcc/config/aarch64/aarch64-arches.def > +++ b/gcc/config/aarch64/aarch64-arches.def > @@ -39,10 +39,12 @@ AARCH64_ARCH("armv8.5-a", generic, V8_5A, 8, (V8_4A, SB, SSBS, PR > AARCH64_ARCH("armv8.6-a", generic, V8_6A, 8, (V8_5A, I8MM, BF16)) > AARCH64_ARCH("armv8.7-a", generic, V8_7A, 8, (V8_6A, LS64)) > AARCH64_ARCH("armv8.8-a", generic, V8_8A, 8, (V8_7A, MOPS)) > +AARCH64_ARCH("armv8.9-a", generic, V8_9A, 8, (V8_8A)) > AARCH64_ARCH("armv8-r", generic, V8R , 8, (V8_4A)) > AARCH64_ARCH("armv9-a", generic, V9A , 9, (V8_5A, SVE2)) > AARCH64_ARCH("armv9.1-a", generic, V9_1A, 9, (V8_6A, V9A)) > AARCH64_ARCH("armv9.2-a", generic, V9_2A, 9, (V8_7A, V9_1A)) > AARCH64_ARCH("armv9.3-a", generic, V9_3A, 9, (V8_8A, V9_2A)) > +AARCH64_ARCH("armv9.4-a", generic, V9_4A, 9, (V8_9A, V9_3A)) > > #undef AARCH64_ARCH > diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc > index be8b7236cf9..cacf8e8ed25 100644 > --- a/gcc/config/aarch64/aarch64-c.cc > +++ b/gcc/config/aarch64/aarch64-c.cc > @@ -206,6 +206,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) > aarch64_def_or_undef (TARGET_LS64, > "__ARM_FEATURE_LS64", pfile); > aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile); > + aarch64_def_or_undef (TARGET_D128, "__ARM_FEATURE_SYSREG128", pfile); > > /* Not for ACLE, but required to keep "float.h" correct if we switch > target between implementations that do or do not support ARMv8.2-A > diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def > index 825f3bf7758..da31f7c32d1 100644 > --- a/gcc/config/aarch64/aarch64-option-extensions.def > +++ b/gcc/config/aarch64/aarch64-option-extensions.def > @@ -151,4 +151,8 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "") > > AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc") > > +AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128") > + > +AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") > + > #undef AARCH64_OPT_EXTENSION > diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h > index 84e6f79ca83..1b3c800ec89 100644 > --- a/gcc/config/aarch64/aarch64.h > +++ b/gcc/config/aarch64/aarch64.h > @@ -219,13 +219,17 @@ enum class aarch64_feature : unsigned char { > #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) > #define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A) > #define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A) > +#define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A) > #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) > #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) > #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) > #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) > +#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A) > #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) > #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) > #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) > +#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128) > +#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE) > > /* AARCH64_FL options necessary for system register implementation. */ > > @@ -388,6 +392,17 @@ enum class aarch64_feature : unsigned char { > /* ARMv8.1-A Adv.SIMD support. */ > #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) > > +/* Armv9.4-A features. */ > +#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) > + > +/* 128-bit System Registers and Instructions from Armv9.4-a are enabled > + through +d128. */ > +#define TARGET_D128 (AARCH64_ISA_D128) > + > +/* Armv8.9-A/9.4-A Translation Hardening Extension system registers are > + enabled through +the. */ > +#define TARGET_THE (AARCH64_ISA_THE) > + > /* Standard register usage. */ > > /* 31 64-bit general purpose registers R0-R30: > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 6e776a0faa1..88327ce9681 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -20722,10 +20722,12 @@ and the features that they enable by default: > @item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} > @item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+ls64} > @item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops} > +@item @samp{armv8.9-a} @tab Armv8.9-a @tab @samp{armv8.8-a} > @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, @samp{+sve2} > @item @samp{armv9.1-a} @tab Armv9.1-A @tab @samp{armv9-a}, @samp{+bf16}, @samp{+i8mm} > @item @samp{armv9.2-a} @tab Armv9.2-A @tab @samp{armv9.1-a}, @samp{+ls64} > @item @samp{armv9.3-a} @tab Armv9.3-A @tab @samp{armv9.2-a}, @samp{+mops} > +@item @samp{armv9.4-a} @tab Armv9.4-A @tab @samp{armv9.3-a} > @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r} > @end multitable > > @@ -21028,6 +21030,10 @@ Enable the Flag Manipulation instructions Extension. > Enable the Pointer Authentication Extension. > @item cssc > Enable the Common Short Sequence Compression instructions. > +@item d128 > +Enable support for 128-bit system register read/write instructions. > +@item the > +Enable support for Armv8.9-a/9.4-a translation hardening extension. > > @end table