From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id ED1533853C02 for ; Tue, 17 Aug 2021 14:37:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ED1533853C02 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8562F31B for ; Tue, 17 Aug 2021 07:37:16 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2D0F13F70D for ; Tue, 17 Aug 2021 07:37:16 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: Re: [PATCH 8/8] aarch64: Add -mtune=neoverse-512tvb References: Date: Tue, 17 Aug 2021 15:37:15 +0100 In-Reply-To: (Richard Sandiford's message of "Tue, 03 Aug 2021 13:06:56 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Aug 2021 14:37:27 -0000 Richard Sandiford writes: > This patch adds an option to tune for Neoverse cores that have > a total vector bandwidth of 512 bits (4x128 for Advanced SIMD > and a vector-length-dependent equivalent for SVE). This is intended > to be a compromise between tuning aggressively for a single core like > Neoverse V1 (which can be too narrow) and tuning for AArch64 cores > in general (which can be too wide). > > -mcpu=neoverse-512tvb is equivalent to -mcpu=neoverse-v1 > -mtune=neoverse-512tvb. > > gcc/ > * doc/invoke.texi: Document -mtune=neoverse-512tvb and > -mcpu=neoverse-512tvb. > * config/aarch64/aarch64-cores.def (neoverse-512tvb): New entry. > * config/aarch64/aarch64-tune.md: Regenerate. > * config/aarch64/aarch64.c (neoverse512tvb_sve_vector_cost) > (neoverse512tvb_sve_issue_info, neoverse512tvb_vec_issue_info) > (neoverse512tvb_vector_cost, neoverse512tvb_tunings): New structures. > (aarch64_adjust_body_cost_sve): Handle -mtune=neoverse-512tvb. > (aarch64_adjust_body_cost): Likewise. I've backported this cut-down version to GCC 10 and 9, so that the option is at least recognised there too. gcc/ * doc/invoke.texi: Document -mtune=neoverse-512tvb and -mcpu=neoverse-512tvb. * config/aarch64/aarch64-cores.def (neoverse-512tvb): New entry. * config/aarch64/aarch64-tune.md: Regenerate. --- gcc/config/aarch64/aarch64-cores.def | 1 + gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/doc/invoke.texi | 24 ++++++++++++++++++++++-- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 9c290292479..fc60e2ae1ac 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -135,6 +135,7 @@ AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, 8_3A, AARCH64_FL_ /* Arm ('A') cores. */ AARCH64_CORE("zeus", zeus, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1) AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1) +AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoversev1, INVALID_IMP, INVALID_CORE, -1) /* Qualcomm ('Q') cores. */ AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 7fda2294b8a..aa68d67bdf4 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index eabeec944e7..72d995cd0cc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16994,8 +16994,9 @@ performance of the code. Permissible values for this option are: @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77}, @samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, -@samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, @samp{neoverse-e1}, -@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{qdf24xx}, +@samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, +@samp{neoverse-e1}, @samp{neoverse-n1}, @samp{neoverse-n2}, +@samp{neoverse-v1}, @samp{neoverse-512tvb}, @samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{octeontx}, @samp{octeontx81}, @samp{octeontx83}, @samp{octeontx2}, @samp{octeontx2t98}, @samp{octeontx2t96} @@ -17015,6 +17016,15 @@ The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55} specify that GCC should tune for a big.LITTLE system. +The value @samp{neoverse-512tvb} specifies that GCC should tune +for Neoverse cores that (a) implement SVE and (b) have a total vector +bandwidth of 512 bits per cycle. In other words, the option tells GCC to +tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic +instructions a cycle and that can execute an equivalent number of SVE +arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE). +This is more general than tuning for a specific core like Neoverse V1 +but is more specific than the default tuning described below. + Additionally on native AArch64 GNU/Linux systems the value @samp{native} tunes performance to the host system. This option has no effect if the compiler is unable to recognize the processor of the host system. @@ -17044,6 +17054,16 @@ by @option{-mtune}). Where this option is used in conjunction with @option{-march} or @option{-mtune}, those options take precedence over the appropriate part of this option. +@option{-mcpu=neoverse-512tvb} is special in that it does not refer +to a specific core, but instead refers to all Neoverse cores that +(a) implement SVE and (b) have a total vector bandwidth of 512 bits +a cycle. Unless overridden by @option{-march}, +@option{-mcpu=neoverse-512tvb} generates code that can run on a +Neoverse V1 core, since Neoverse V1 is the first Neoverse core with +these properties. Unless overridden by @option{-mtune}, +@option{-mcpu=neoverse-512tvb} tunes code in the same way as for +@option{-mtune=neoverse-512tvb}. + @item -moverride=@var{string} @opindex moverride Override tuning decisions made by the back-end in response to a