From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2D44D3858C50; Thu, 30 May 2024 20:16:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2D44D3858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2D44D3858C50 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717100183; cv=none; b=iYTLcouARxSAa7CRIpPbt1DKK2FzZpmxhWgYguS2sEODXSBsPZN42wpBLKXNPn0iEB7UkI/Zemq0sUOwRZNnn4tQgOVdhtBOUGUXzi2fAqDf0WIc2gr6wVHwIzYNnNvIH2WAKzos2a347LvOwYEyIrvcFPF41SWYxJlFy3zKZbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717100183; c=relaxed/simple; bh=eJwFJOEBcGoAAByay7gumDQk9j5FAD9sJKUFaezjKuU=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=J75fNHzjeO4AAVcxSRONXaR7M1bU9rJdsWQysTmMetX2sdIjHKkyQwagHWlmvSMXKOhqUnJzgb0xUUwpF4AfEtaCaTufyTgoNQO9KVhCnQdU3QfgD8IhTNzaXx/UG7Jz2VaTH/eNja6V3v7Aa/qKOlVLikRLjoCSwSOt2v3mXoo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1FF191424; Thu, 30 May 2024 13:16:46 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E83B63F641; Thu, 30 May 2024 13:16:20 -0700 (PDT) From: Richard Sandiford To: Tamar Christina Mail-Followup-To: Tamar Christina ,gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, ktkachov@gcc.gnu.org, richard.sandiford@arm.com Cc: gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, ktkachov@gcc.gnu.org Subject: Re: [PATCH 4/4]AArch64: enable new predicate tuning for Neoverse cores. References: Date: Thu, 30 May 2024 21:16:19 +0100 In-Reply-To: (Tamar Christina's message of "Tue, 28 May 2024 10:49:16 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-20.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tamar Christina writes: > Hi All, > > This enables the new tuning flag for Neoverse V1, Neoverse V2 and Neoverse N2. > It is kept off for generic codegen. > > Note the reason for the +sve even though they are in aarch64-sve.exp is if the > testsuite is ran with a forced SVE off option, e.g. -march=armv8-a+nosve then > the intrinsics end up being disabled because the -march is preferred over the > -mcpu even though the -mcpu comes later. > > This prevents the tests from failing in such runs. IMO we should just skip aarch64-sve.exp if the options explicitly disable SVE. But that's separate work. I'll try it once this patch is in. > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/tuning_models/neoversen2.h (neoversen2_tunings): Add > AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. > * config/aarch64/tuning_models/neoversev1.h (neoversev1_tunings): Add > AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. > * config/aarch64/tuning_models/neoversev2.h (neoversev2_tunings): Add > AARCH64_EXTRA_TUNE_AVOID_PRED_RMW. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/pred_clobber_1.c: New test. > * gcc.target/aarch64/sve/pred_clobber_2.c: New test. > * gcc.target/aarch64/sve/pred_clobber_3.c: New test. > * gcc.target/aarch64/sve/pred_clobber_4.c: New test. > > --- > diff --git a/gcc/config/aarch64/tuning_models/neoversen2.h b/gcc/config/aarch64/tuning_models/neoversen2.h > index 7e799bbe762fe862e31befed50e54040a7fd1f2f..be9a48ac3adc097f967c217fe09dcac194d7d14f 100644 > --- a/gcc/config/aarch64/tuning_models/neoversen2.h > +++ b/gcc/config/aarch64/tuning_models/neoversen2.h > @@ -236,7 +236,8 @@ static const struct tune_params neoversen2_tunings = > (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND > | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS > | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS > - | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ > + | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT > + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ > &generic_prefetch_tune, > AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ > AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ > diff --git a/gcc/config/aarch64/tuning_models/neoversev1.h b/gcc/config/aarch64/tuning_models/neoversev1.h > index 9363f2ad98a5279cc99f2f9b1509ba921d582e84..0fc41ce6a41b3135fa06d2bda1f517fdf4f8dbcf 100644 > --- a/gcc/config/aarch64/tuning_models/neoversev1.h > +++ b/gcc/config/aarch64/tuning_models/neoversev1.h > @@ -227,7 +227,8 @@ static const struct tune_params neoversev1_tunings = > (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS > | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS > | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT > - | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ > + | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND > + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ > &generic_prefetch_tune, > AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ > AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ > diff --git a/gcc/config/aarch64/tuning_models/neoversev2.h b/gcc/config/aarch64/tuning_models/neoversev2.h > index bc01ed767c9b690504eb98456402df5d9d64eee3..f76e4ef358f7dfb9c7d7b470ea7240eaa2120f8e 100644 > --- a/gcc/config/aarch64/tuning_models/neoversev2.h > +++ b/gcc/config/aarch64/tuning_models/neoversev2.h > @@ -236,7 +236,8 @@ static const struct tune_params neoversev2_tunings = > (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND > | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS > | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS > - | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ > + | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT > + | AARCH64_EXTRA_TUNE_AVOID_PRED_RMW), /* tune_flags. */ > &generic_prefetch_tune, > AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ > AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c > new file mode 100644 > index 0000000000000000000000000000000000000000..934a00a38531c5fd4139d99ff33414904b2c104f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_1.c > @@ -0,0 +1,22 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mcpu=neoverse-n2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#pragma GCC target "+sve" > + > +#include > + > +extern void use(svbool_t); > + > +/* > +** foo: > +** ... > +** ptrue p([1-9][0-9]?).b, all Might be better to make this p([1-3]), so that we disallow any registers that would cause a spill. OK with that change, thanks. Richard > +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h > +** ... > +*/ > +void foo (svuint16_t a, uint16_t b) > +{ > + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); > + use (p0); > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c > new file mode 100644 > index 0000000000000000000000000000000000000000..58badb66a43b1ac50eeec153b9cac44fc831b145 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_2.c > @@ -0,0 +1,22 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mcpu=neoverse-v2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#pragma GCC target "+sve" > + > +#include > + > +extern void use(svbool_t); > + > +/* > +** foo: > +** ... > +** ptrue p([1-9][0-9]?).b, all > +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h > +** ... > +*/ > +void foo (svuint16_t a, uint16_t b) > +{ > + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); > + use (p0); > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c > new file mode 100644 > index 0000000000000000000000000000000000000000..c67c2bd3422e0bb0c694b5fe0adf0d83e4d967c6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_3.c > @@ -0,0 +1,23 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mcpu=neoverse-v1" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#pragma GCC target "+sve" > + > +#include > + > +extern void use(svbool_t); > + > +/* > +** foo: > +** ... > +** ptrue p([1-9][0-9]?).b, all > +** cmplo p0.h, p\1/z, z0.h, z[0-9]+.h > +** ... > +*/ > +void foo (svuint16_t a, uint16_t b) > +{ > + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); > + use (p0); > +} > + > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c > new file mode 100644 > index 0000000000000000000000000000000000000000..c0120afe5d523eff8297fadd4fc4c678676413d6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c > @@ -0,0 +1,22 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#pragma GCC target "+sve" > + > +#include > + > +extern void use(svbool_t); > + > +/* > +** foo: > +** ... > +** ptrue p0.b, all > +** cmplo p0.h, p0/z, z0.h, z[0-9]+.h > +** ... > +*/ > +void foo (svuint16_t a, uint16_t b) > +{ > + svbool_t p0 = svcmplt_n_u16 (svptrue_b16 (), a, b); > + use (p0); > +}