From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A4A693858D20 for ; Thu, 14 Dec 2023 16:24:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A4A693858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A4A693858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702571063; cv=none; b=YKURWGTqRxMQm1QiQYcznGkTVExaltNZLKLb+sN1X42AGkt60xU89evtO117IsvmIjtcFnlUnFZ0XZYinXVFM3uPR7Jzm7Jgqr5XyvSY6+JuPaZ8Ee+ao/3k5fdFog/eHSlqKnGJ+6/XeJt8B0v9fS082B7hE6IjH89SZac5e0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702571063; c=relaxed/simple; bh=OipH63Rjxj5o/pVUNAZ3hLReuvuu7itcQTo2T3UPJpY=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=HzTwZzun1O8hGeup25NPL80Oitrafe9e9WBfWTNDhkMxQb/3OKUuNLKlZJPWX3ZJ1Vswy1w2uX8gNT736NwQWxnJNigJIU572GhoApJSx+5+yzaoWFHDiCi24Q1ZhlfrzZ68JaaTTIRg96a1tQFKnILUJWpn5sPXol2/iNUgT5Q= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6932C15; Thu, 14 Dec 2023 08:25:07 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8159A3F5A1; Thu, 14 Dec 2023 08:24:21 -0800 (PST) From: Richard Sandiford To: Robin Dapp Mail-Followup-To: Robin Dapp ,gcc-patches , Richard Biener , richard.sandiford@arm.com Cc: gcc-patches , Richard Biener Subject: Re: [PATCH] expmed: Get vec_extract element mode from insn_data, [PR112999] References: <67552cb3-e08e-4003-a45d-9ed64bd7da43@gmail.com> <44f657b3-503e-4e76-9aa9-0ab3b18225fd@gmail.com> Date: Thu, 14 Dec 2023 16:24:20 +0000 In-Reply-To: <44f657b3-503e-4e76-9aa9-0ab3b18225fd@gmail.com> (Robin Dapp's message of "Thu, 14 Dec 2023 17:13:55 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-21.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Robin Dapp writes: >> It looks like: >> >> FOR_EACH_MODE_FROM (new_mode, new_mode) >> if (known_eq (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (GET_MODE (op0))) >> && known_eq (GET_MODE_UNIT_SIZE (new_mode), GET_MODE_SIZE (tmode)) >> && targetm.vector_mode_supported_p (new_mode) >> && targetm.modes_tieable_p (GET_MODE (op0), new_mode)) >> break; >> >> should at least test whether the bitpos is a multiple of >> GET_MODE_UNIT_SIZE (new_mode), otherwise the new mode isn't really >> better. Arguably it should also test whether bitnum is equal >> to GET_MODE_UNIT_SIZE (new_mode). >> >> Not sure whether there'll be any fallout from that, but it seems >> worth trying. > > Thanks, bootstrapped and regtested the attached v2 without fallout > on x86, aarch64 and power10. Tested on riscv. Nice. No fallout on three targets seems promising. > Regards > Robin > > Subject: [PATCH v2] expmed: Compare unit_precision for better mode. > > In extract_bit_field_1 we try to get a better vector mode before > extracting from it. Better refers to the case when the requested target > mode does not equal the inner mode of the vector to extract from and we > have an equivalent tieable vector mode with a fitting inner mode. > > On riscv this triggered an ICE (PR112999) because we would take the > detour of extracting from a mask-mode vector via a vector integer mode. > One element of that mode could be subreg-punned with TImode which, in > turn, would need to be operated on in DImode chunks. > > This patch adds > > && known_eq (bitsize, GET_MODE_UNIT_PRECISION (new_mode)) > && multiple_p (bitnum, GET_MODE_UNIT_PRECISION (new_mode)) > > to the list of criteria for a better mode. > > gcc/ChangeLog: > > PR target/112999 > > * expmed.cc (extract_bit_field_1): Ensure better mode > has fitting unit_precision. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/pr112999.c: New test. OK, thanks. Richard > --- > gcc/expmed.cc | 2 ++ > .../gcc.target/riscv/rvv/autovec/pr112999.c | 17 +++++++++++++++++ > 2 files changed, 19 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c > > diff --git a/gcc/expmed.cc b/gcc/expmed.cc > index d75314096b4..05331dd5d82 100644 > --- a/gcc/expmed.cc > +++ b/gcc/expmed.cc > @@ -1745,6 +1745,8 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, > FOR_EACH_MODE_FROM (new_mode, new_mode) > if (known_eq (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (GET_MODE (op0))) > && known_eq (GET_MODE_UNIT_SIZE (new_mode), GET_MODE_SIZE (tmode)) > + && known_eq (bitsize, GET_MODE_UNIT_PRECISION (new_mode)) > + && multiple_p (bitnum, GET_MODE_UNIT_PRECISION (new_mode)) > && targetm.vector_mode_supported_p (new_mode) > && targetm.modes_tieable_p (GET_MODE (op0), new_mode)) > break; > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c > new file mode 100644 > index 00000000000..c049c5a0386 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */ > + > +int a[1024]; > +int b[1024]; > + > +_Bool > +fn1 () > +{ > + _Bool tem; > + for (int i = 0; i < 1024; ++i) > + { > + tem = !a[i]; > + b[i] = tem; > + } > + return tem; > +}