[patch][aarch64]: add support for fabd in sve

[patch][aarch64]: add support for fabd in sve

[Sylvia Taylor]

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Greetings,

This patch adds support in SVE to combine:
- fsub and fabs into fabd

fsub    z0.s, z0.s, z1.s
fabs    z0.s, p1/m, z0.s
---
fabd    z0.s, p1/m, z0.s, z1.s

Bootstrapped and tested on aarch64-none-linux-gnu.

Ok for trunk? If yes, I don't have commit rights,
so if someone can please commit it on my behalf.

Cheers,
Syl

gcc/ChangeLog:

2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>

	* config/aarch64/aarch64-sve.md
	(*fabd<mode>3): New.

gcc/testsuite/ChangeLog:

2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>

	* gcc.target/aarch64/sve/fabd.c: New.

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diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 3f39c4c5b63798515ed4c109836b036573de4aad..4c46aa55dfc174424ff47447f26c44b038d768ea 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2528,6 +2528,19 @@
   "<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
 )
 
+(define_insn "*fabd<mode>3"
+  [(set (match_operand:SVE_F 0 "register_operand" "=w")
+	(unspec:SVE_F
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl")
+	   (abs:SVE_F
+	    (minus:SVE_F
+		(match_operand:SVE_F 2 "register_operand" "0")
+		(match_operand:SVE_F 3 "register_operand" "w")))]
+	UNSPEC_MERGE_PTRUE))]
+  "TARGET_SVE"
+  "fabd\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>"
+)
+
 ;; Unpredicated FRINTy.
 (define_expand "<frint_pattern><mode>2"
   [(set (match_operand:SVE_F 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fabd.c b/gcc/testsuite/gcc.target/aarch64/sve/fabd.c
new file mode 100644
index 0000000000000000000000000000000000000000..13ad83be24ceb0d3319cb3bcfdbd6372b4d1a48e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/fabd.c
@@ -0,0 +1,35 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3 --save-temps" } */
+
+#define N 16
+
+typedef float *__restrict__ vnx4sf;
+typedef double *__restrict__ vnx2df;
+typedef _Float16 *__restrict__ vnx8hf_a;
+typedef __fp16 *__restrict__ vnx8hf_b;
+
+extern float fabsf (float);
+extern double fabs (double);
+
+#define FABD(type, abs, n)				\
+	void fabd_##type (type res, type a, type b)	\
+	{						\
+	    int i;					\
+	    for (i = 0; i < n; i++)			\
+		res[i] = abs (a[i] - b[i]);		\
+	}
+
+#define TEST_SVE_F_MODES(FUNC)	\
+  FUNC (vnx2df, fabs, N)	\
+  FUNC (vnx4sf, fabsf, N)	\
+  FUNC (vnx8hf_a, fabsf, N)	\
+  FUNC (vnx8hf_b, fabsf, N)	\
+
+TEST_SVE_F_MODES (FABD)
+
+/* { dg-final { scan-assembler "fabd" } } */
+/* { dg-final { scan-assembler-not "fsub" } } */
+/* { dg-final { scan-assembler-not "fabs" } } */
+/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */

Re: [patch][aarch64]: add support for fabd in sve

[Richard Sandiford]

Sylvia Taylor <Sylvia.Taylor@arm.com> writes:
> Greetings,
>
> This patch adds support in SVE to combine:
> - fsub and fabs into fabd
>
> fsub    z0.s, z0.s, z1.s
> fabs    z0.s, p1/m, z0.s
> ---
> fabd    z0.s, p1/m, z0.s, z1.s
>
> Bootstrapped and tested on aarch64-none-linux-gnu.
>
> Ok for trunk? If yes, I don't have commit rights,
> so if someone can please commit it on my behalf.
>
> Cheers,
> Syl
>
> gcc/ChangeLog:
>
> 2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>
>
> 	* config/aarch64/aarch64-sve.md
> 	(*fabd<mode>3): New.
>
> gcc/testsuite/ChangeLog:
>
> 2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>
>
> 	* gcc.target/aarch64/sve/fabd.c: New.

Thanks, applied as r271785.  (I renamed the test to fabd_1.c while
committing, to make it more consistent with the others in that directory.)

Richard