From: Richard Sandiford <richard.sandiford@arm.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 01/21] aarch64: Generalise require_immediate_lane_index
Date: Fri, 17 Nov 2023 17:24:05 +0000 [thread overview]
Message-ID: <mptzfzcthsa.fsf@arm.com> (raw)
In-Reply-To: <mpt4jhkuwdr.fsf@arm.com> (Richard Sandiford's message of "Fri, 17 Nov 2023 17:23:28 +0000")
require_immediate_lane_index previously hard-coded the assumption
that the group size is determined by the argument immediately before
the index. However, for SME, there are cases where it should be
determined by an earlier argument instead.
gcc/
* config/aarch64/aarch64-sve-builtins.h:
(function_checker::require_immediate_lane_index): Add an argument
for the index of the indexed vector argument.
* config/aarch64/aarch64-sve-builtins.cc
(function_checker::require_immediate_lane_index): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(ternary_bfloat_lane_base::check): Update accordingly.
(ternary_qq_lane_base::check): Likewise.
(binary_lane_def::check): Likewise.
(binary_long_lane_def::check): Likewise.
(ternary_lane_def::check): Likewise.
(ternary_lane_rotate_def::check): Likewise.
(ternary_long_lane_def::check): Likewise.
(ternary_qq_lane_rotate_def::check): Likewise.
---
.../aarch64/aarch64-sve-builtins-shapes.cc | 16 ++++++++--------
gcc/config/aarch64/aarch64-sve-builtins.cc | 18 ++++++++++++------
gcc/config/aarch64/aarch64-sve-builtins.h | 3 ++-
3 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
index af816c4c9e7..1646afc7a0d 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
@@ -941,7 +941,7 @@ struct ternary_bfloat_lane_base
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (3, N);
+ return c.require_immediate_lane_index (3, 2, N);
}
};
@@ -956,7 +956,7 @@ struct ternary_qq_lane_base
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (3, 4);
+ return c.require_immediate_lane_index (3, 0);
}
};
@@ -1123,7 +1123,7 @@ struct binary_lane_def : public overloaded_base<0>
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (2);
+ return c.require_immediate_lane_index (2, 1);
}
};
SHAPE (binary_lane)
@@ -1162,7 +1162,7 @@ struct binary_long_lane_def : public overloaded_base<0>
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (2);
+ return c.require_immediate_lane_index (2, 1);
}
};
SHAPE (binary_long_lane)
@@ -2817,7 +2817,7 @@ struct ternary_lane_def : public overloaded_base<0>
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (3);
+ return c.require_immediate_lane_index (3, 2);
}
};
SHAPE (ternary_lane)
@@ -2845,7 +2845,7 @@ struct ternary_lane_rotate_def : public overloaded_base<0>
bool
check (function_checker &c) const override
{
- return (c.require_immediate_lane_index (3, 2)
+ return (c.require_immediate_lane_index (3, 2, 2)
&& c.require_immediate_one_of (4, 0, 90, 180, 270));
}
};
@@ -2868,7 +2868,7 @@ struct ternary_long_lane_def
bool
check (function_checker &c) const override
{
- return c.require_immediate_lane_index (3);
+ return c.require_immediate_lane_index (3, 2);
}
};
SHAPE (ternary_long_lane)
@@ -2965,7 +2965,7 @@ struct ternary_qq_lane_rotate_def : public overloaded_base<0>
bool
check (function_checker &c) const override
{
- return (c.require_immediate_lane_index (3, 4)
+ return (c.require_immediate_lane_index (3, 0)
&& c.require_immediate_one_of (4, 0, 90, 180, 270));
}
};
diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc
index 161a14edde7..75a51565ed2 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -2440,20 +2440,26 @@ function_checker::require_immediate_enum (unsigned int rel_argno, tree type)
return false;
}
-/* Check that argument REL_ARGNO is suitable for indexing argument
- REL_ARGNO - 1, in groups of GROUP_SIZE elements. REL_ARGNO counts
- from the end of the predication arguments. */
+/* The intrinsic conceptually divides vector argument REL_VEC_ARGNO into
+ groups of GROUP_SIZE elements. Return true if argument REL_ARGNO is
+ a suitable constant index for selecting one of these groups. The
+ selection happens within a 128-bit quadword, rather than the whole vector.
+
+ REL_ARGNO and REL_VEC_ARGNO count from the end of the predication
+ arguments. */
bool
function_checker::require_immediate_lane_index (unsigned int rel_argno,
+ unsigned int rel_vec_argno,
unsigned int group_size)
{
unsigned int argno = m_base_arg + rel_argno;
if (!argument_exists_p (argno))
return true;
- /* Get the type of the previous argument. tree_argument_type wants a
- 1-based number, whereas ARGNO is 0-based. */
- machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, argno));
+ /* Get the type of the vector argument. tree_argument_type wants a
+ 1-based number, whereas VEC_ARGNO is 0-based. */
+ unsigned int vec_argno = m_base_arg + rel_vec_argno;
+ machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, vec_argno + 1));
gcc_assert (VECTOR_MODE_P (mode));
unsigned int nlanes = 128 / (group_size * GET_MODE_UNIT_BITSIZE (mode));
return require_immediate_range (rel_argno, 0, nlanes - 1);
diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h
index a301570b82e..99bfd906a07 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins.h
@@ -463,7 +463,8 @@ public:
bool require_immediate_either_or (unsigned int, HOST_WIDE_INT,
HOST_WIDE_INT);
bool require_immediate_enum (unsigned int, tree);
- bool require_immediate_lane_index (unsigned int, unsigned int = 1);
+ bool require_immediate_lane_index (unsigned int, unsigned int,
+ unsigned int = 1);
bool require_immediate_one_of (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT,
HOST_WIDE_INT, HOST_WIDE_INT);
bool require_immediate_range (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT);
--
2.25.1
next prev parent reply other threads:[~2023-11-17 17:24 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 17:23 [PATCH 00/21] aarch64: Add support for SME Richard Sandiford
2023-11-17 17:24 ` Richard Sandiford [this message]
2023-11-17 17:24 ` [PATCH 02/21] aarch64: Add a result_mode helper function Richard Sandiford
2023-11-17 17:24 ` [PATCH 03/21] aarch64: Use SVE's RDVL instruction Richard Sandiford
2023-11-17 17:24 ` [PATCH 04/21] aarch64: Make AARCH64_FL_SVE requirements explicit Richard Sandiford
2023-11-17 17:25 ` [PATCH 05/21] aarch64: Add group suffixes to SVE intrinsics Richard Sandiford
2023-11-17 17:25 ` [PATCH 06/21] aarch64: Add tuple forms of svreinterpret Richard Sandiford
2023-11-17 17:25 ` [PATCH 07/21] aarch64: Add arm_streaming(_compatible) attributes Richard Sandiford
2023-11-17 17:25 ` [PATCH 08/21] aarch64: Add +sme Richard Sandiford
2023-11-17 17:25 ` [PATCH 09/21] aarch64: Distinguish streaming-compatible AdvSIMD insns Richard Sandiford
2023-11-17 17:26 ` [PATCH 10/21] aarch64: Mark relevant SVE instructions as non-streaming Richard Sandiford
2023-11-17 17:26 ` [PATCH 11/21] aarch64: Switch PSTATE.SM around calls Richard Sandiford
2023-11-17 17:26 ` [PATCH 12/21] aarch64: Add support for SME ZA attributes Richard Sandiford
2023-11-17 17:26 ` [PATCH 13/21] aarch64: Add a register class for w12-w15 Richard Sandiford
2023-11-17 17:27 ` [PATCH 14/21] aarch64: Add a VNx1TI mode Richard Sandiford
2023-11-17 17:27 ` [PATCH 15/21] aarch64: Generalise unspec_based_function_base Richard Sandiford
2023-11-17 17:27 ` [PATCH 16/21] aarch64: Generalise _m rules for SVE intrinsics Richard Sandiford
2023-11-17 17:29 ` [PATCH 17/21] aarch64: Add support for <arm_sme.h> Richard Sandiford
2023-11-17 17:30 ` [PATCH 18/21] aarch64: Add support for __arm_locally_streaming Richard Sandiford
2023-11-17 17:30 ` [PATCH 19/21] aarch64: Handle PSTATE.SM across abnormal edges Richard Sandiford
2023-11-17 17:30 ` [PATCH 20/21] aarch64: Enforce inlining restrictions for SME Richard Sandiford
2023-11-17 17:30 ` [PATCH 21/21] aarch64: Update sibcall handling " Richard Sandiford
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