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From: Richard Sandiford <richard.sandiford@arm.com>
To: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
Mail-Followup-To: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>,
 gcc Patches <gcc-patches@gcc.gnu.org>, richard.sandiford@arm.com
Cc: gcc Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [SVE] PR96463 - Optimise svld1rq from vectors
References: <CAAgBjMmAJek1O=pFkRNx9jn2DAzD-0AV57ASq0cyP+aDmg+9sg@mail.gmail.com>
Date: Thu, 02 Dec 2021 17:41:31 +0000
In-Reply-To: <CAAgBjMmAJek1O=pFkRNx9jn2DAzD-0AV57ASq0cyP+aDmg+9sg@mail.gmail.com>
 (Prathamesh Kulkarni's message of "Thu, 2 Dec 2021 16:20:40 +0530")
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Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> writes:
> Hi Richard,
> I have attached a WIP untested patch for PR96463.
> IIUC, the PR suggests to transform
> lhs =3D svld1rq ({-1, -1, ...}, &v[0])
> into:
> lhs =3D vec_perm_expr<v, v, {0, 0, ...}>
> if v is vector of 4 elements, and each element is 32 bits on little
> endian target ?
>
> I am sorry if this sounds like a silly question, but I am not sure how
> to convert a vector of type int32x4_t into svint32_t ? In the patch, I
> simply used NOP_EXPR (which I expected to fail), and gave type error
> during gimple verification:

It should be possible in principle to have a VEC_PERM_EXPR in which
the operands are Advanced SIMD vectors and the result is an SVE vector.

E.g., the dup in the PR would be something like this:

foo (int32x4_t a)
{
  svint32_t _2;

  _2 =3D VEC_PERM_EXPR <x_1(D), x_1(D), { 0, 1, 2, 3, 0, 1, 2, 3, ... }>;
  return _2;
}

where the final operand can be built using:

  int source_nelts =3D TYPE_VECTOR_SUBPARTS (=E2=80=A6rhs type=E2=80=A6).to=
_constant ();
  vec_perm_builder sel (TYPE_VECTOR_SUBPARTS (=E2=80=A6lhs type=E2=80=A6), =
source_nelts, 1);
  for (int i =3D 0; i < source_nelts; ++i)
    sel.quick_push (i);

I'm not sure how well-tested that combination is though.  It might need
changes to target-independent code.

Thanks,
Richard