From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59901 invoked by alias); 21 May 2015 16:53:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 59843 invoked by uid 89); 21 May 2015 16:53:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.4 required=5.0 tests=AWL,BAYES_50,KAM_STOCKGEN,SPF_PASS,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: fencepost.gnu.org Received: from fencepost.gnu.org (HELO fencepost.gnu.org) (208.118.235.10) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 21 May 2015 16:53:33 +0000 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44310) by fencepost.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1YvTit-0008GG-5h for gcc-patches@gnu.org; Thu, 21 May 2015 12:53:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YvTip-0007Sy-Vr for gcc-patches@gnu.org; Thu, 21 May 2015 12:53:30 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:49909) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvTip-0007Qx-Mn for gcc-patches@gnu.org; Thu, 21 May 2015 12:53:27 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-19.uk.mimecast.lan; Thu, 21 May 2015 17:53:24 +0100 Received: from e104437-lin ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 21 May 2015 17:53:24 +0100 From: Jiong Wang To: gcc-patches Subject: [AArch64][TLSLE][N/N] Implement local executable mode for all memory model Date: Thu, 21 May 2015 16:58:00 -0000 Message-ID: MIME-Version: 1.0 X-MC-Unique: N67xCeYfTcuwS5YqlWKPIA-1 Content-Type: multipart/mixed; boundary="=-=-=" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 146.101.78.143 X-SW-Source: 2015-05/txt/msg02003.txt.bz2 --=-=-= Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-length: 1835 4 instruction sequences can be implemented for AArch64 TLS LE model based on relocations provided. These instruction sequences are the same for tiny/small/large, We just need to choose the most efficient one to use accoding to tls size. the 12bit version give us 4K TLS size, 24bit give us 16M, 32bit give us 4G while 48bit gives us 256TB. sequence 1 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D add t0, tp, #:tprel_lo12:x1 R_AARCH64_TLSLE_ADD_TPREL_LO12 = x1 sequence 2 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D add t0, tp, #:tprel_hi12:x1, lsl #12 R_AARCH64_TLSLE_ADD_TPREL_HI12 = x2 add t0, #:tprel_lo12_nc:x1 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC = x2 sequence 2 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D movz t0, #:tprel_g1:x3 R_AARCH64_TLSLE_MOVW_TPREL_G1 = x3 movk t0, #:tprel_g0_nc:x3 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = x3 add t0, tp, t0 sequence 4 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D movz t0, #:tprel_g2:x4 R_AARCH64_TLSLE_MOVW_TPREL_G2 = x4 movk t0, #:tprel_g1_nc:x4 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC = x4 movk t0, #:tprel_g0_nc:x4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = x4 add t0, t0, tp OK for trunk? 2015-05-14 Jiong Wang gcc/ * config/aarch64/aarch64.c (aarch64_print_operand): Support tls_size. * config/aarch64/aarch64.md (tlsle): Choose proper instruction sequences. (tlsle_): New define_insn. (tlsle_movsym_): Ditto. * config/aarch64/constraints.md (Uta): New constraint. (Utb): Ditto. (Utc): Ditto. (Utd): Ditto. gcc/testsuite/ * gcc.target/aarch64/tlsle.c: New test source. * gcc.target/aarch64/tlsle12.c: New testcase. * gcc.target/aarch64/tlsle24.c: New testcase. * gcc.target/aarch64/tlsle32.c: New testcase. --=20 Regards, Jiong --=-=-= Content-Type: text/x-diff; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename=2.patch Content-length: 6764 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e6aa0e1..569f22d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4450,7 +4450,11 @@ aarch64_print_operand (FILE *f, rtx x, char code) break; =20 case SYMBOL_TLSLE: - asm_fprintf (asm_out_file, ":tprel_lo12_nc:"); + if (aarch64_tls_size <=3D 12) + /* Make sure TLS offset fit into 12bit. */ + asm_fprintf (asm_out_file, ":tprel_lo12:"); + else + asm_fprintf (asm_out_file, ":tprel_lo12_nc:"); break; =20 case SYMBOL_TINY_GOT: diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b1425a3..8b061ba 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4304,21 +4304,60 @@ "" { machine_mode mode =3D GET_MODE (operands[0]); - emit_insn ((mode =3D=3D DImode - ? gen_tlsle_di - : gen_tlsle_si) (operands[0], operands[1], operands[2])); + rtx (*gen_tlsle_si_special) (rtx , rtx , rtx); + rtx (*gen_tlsle_di_special) (rtx , rtx , rtx); + + /* For tls offset <=3D24, utilize add to load 12bit offset. */ + if (aarch64_tls_size <=3D 24) + { + gen_tlsle_si_special =3D gen_tlsle_si; + gen_tlsle_di_special =3D gen_tlsle_di; + + emit_insn ((mode =3D=3D DImode + ? gen_tlsle_di_special + : gen_tlsle_si_special) (operands[0], operands[1], + operands[2])); + DONE; + } + /* Load the sym's offset into operands[0]. */ + else if (aarch64_tls_size <=3D 48) + emit_insn (mode =3D=3D DImode + ? gen_tlsle_movsym_di (operands[0], operands[2]) + : gen_tlsle_movsym_si (operands[0], operands[2])); + else + gcc_unreachable (); + + /* Add base address from tp. */ + emit_insn (mode =3D=3D DImode + ? gen_adddi3 (operands[0], operands[0], operands[1]) + : gen_addsi3 (operands[0], operands[0], operands[1])); + DONE; }) =20 (define_insn "tlsle_" - [(set (match_operand:P 0 "register_operand" "=3Dr") - (unspec:P [(match_operand:P 1 "register_operand" "r") - (match_operand 2 "aarch64_tls_le_symref" "S")] + [(set (match_operand:P 0 "register_operand" "=3Dr, r") + (unspec:P [(match_operand:P 1 "register_operand" "r, r") + (match_operand 2 "aarch64_tls_le_symref" "Uta, Utb")] UNSPEC_TLSLE))] "" - "add\\t%0, %1, #%G2, lsl #12\;add\\t%0, %0, #%L2" - [(set_attr "type" "alu_sreg") - (set_attr "length" "8")] + "@ + add\\t%0, %1, #%L2 + add\\t%0, %1, #%G2, lsl #12\;add\\t%0, %0, #%L2" + [(set_attr "type" "alu_sreg, multiple") + (set_attr "length" "4, 8")] +) + +(define_insn "tlsle_movsym_" + [(set (match_operand:P 0 "register_operand" "=3Dr, r") + (unspec:P [(match_operand 1 "aarch64_tls_le_symref" "Utc, Utd")] + UNSPEC_TLSLE))] + "" + "@ + movz\\t%0, #:tprel_g1:%1\;movk\\t%0, #:tprel_g0_nc:%1 + movz\\t%0, #:tprel_g2:%1\;movk\\t%0, #:tprel_g1_nc:%1\;movk\\t%0, #:tprel_g0_nc:%1" + [(set_attr "type" "multiple, multiple") + (set_attr "length" "8, 12")] ) =20 (define_insn "tlsdesc_small_" diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constra= ints.md index 5b189ea..58fe082 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -109,6 +109,30 @@ A constraint that matches the immediate constant -1." (match_test "op =3D=3D constm1_rtx")) =20 +(define_constraint "Uta" + "A constraint that matches an absolute symbolic address which needs 12bi= t" + (and (match_code "const,symbol_ref,label_ref") + (and (match_test "aarch64_symbolic_address_p (op)") + (match_test "aarch64_tls_size <=3D 12")))) + +(define_constraint "Utb" + "A constraint that matches an absolute symbolic address which needs 24bi= t" + (and (match_code "const,symbol_ref,label_ref") + (and (match_test "aarch64_symbolic_address_p (op)") + (match_test "aarch64_tls_size > 12 && aarch64_tls_size <=3D 24")))) + +(define_constraint "Utc" + "A constraint that matches an absolute symbolic address which needs 32bi= t" + (and (match_code "const,symbol_ref,label_ref") + (and (match_test "aarch64_symbolic_address_p (op)") + (match_test "aarch64_tls_size > 24 && aarch64_tls_size <=3D 32")))) + +(define_constraint "Utd" + "A constraint that matches an absolute symbolic address which needs 48bi= t" + (and (match_code "const,symbol_ref,label_ref") + (and (match_test "aarch64_symbolic_address_p (op)") + (match_test "aarch64_tls_size > 32 && aarch64_tls_size <=3D 48")))) + (define_constraint "Ui1" "@internal A constraint that matches the immediate constant +1." diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle.c b/gcc/testsuite/gcc.t= arget/aarch64/tlsle.c new file mode 100644 index 0000000..d92281b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle.c @@ -0,0 +1,14 @@ +void abort (void); + +__thread int t0 =3D 0x10; +__thread int t1 =3D 0x10; + +int +main (int argc, char **argv) +{ + if (t0 !=3D t1) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle12.c b/gcc/testsuite/gcc= .target/aarch64/tlsle12.c new file mode 100644 index 0000000..459a20b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle12.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=3Dlocal-exec -mtls-size=3D12 --save= -temps" } */ + +#include "tlsle.c" + +/* { dg-final { scan-assembler-times "#:tprel_lo12" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle24.c b/gcc/testsuite/gcc= .target/aarch64/tlsle24.c new file mode 100644 index 0000000..c7627d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle24.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=3Dlocal-exec -mtls-size=3D24 --save= -temps" } */ + +#include "tlsle.c" + +/* { dg-final { scan-assembler-times "#:tprel_lo12_nc" 2 } } */ +/* { dg-final { scan-assembler-times "#:tprel_hi12" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle32.c b/gcc/testsuite/gcc= .target/aarch64/tlsle32.c new file mode 100644 index 0000000..4180654 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle32.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=3Dlocal-exec -mtls-size=3D32 --save= -temps" } */ + +#include "tlsle.c" + +/* { dg-final { scan-assembler-times "#:tprel_g1" 2 } } */ +/* { dg-final { scan-assembler-times "#:tprel_g0_nc" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ --=-=-=--