From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by sourceware.org (Postfix) with ESMTPS id 754023857415 for ; Thu, 22 Jul 2021 06:38:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 754023857415 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id 5DBFA2255D; Thu, 22 Jul 2021 06:38:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1626935901; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=vzAPRnb+T/4MuIME7vk+7W8oCoLPKF7y0l6uKHsoRRc=; b=TI/bBWhDWIL4qTx5mjNxOawi7W2HN6ONjjzpXp025U8DXHgQ+ZpOApXfDU5u9Rzra9gGjQ 1FvfQnt3F1RXmto8OtiaP3mrQ1BchnDdQGNZSoQbrtI4cRZ022WInSMmd8DSN0Nx0w40Kp WVK5n5PR/L+dIbGzDenT/ZyN2sghR5w= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1626935901; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=vzAPRnb+T/4MuIME7vk+7W8oCoLPKF7y0l6uKHsoRRc=; b=DODXEwJw4H4Llt94yoiXQeE/TW9xguYE0U0KGOR/sLXmSADp6Tp0fUsxbAhLrPtp8H2B5q 9Rmu7YkJELPestDw== Received: from murzim.suse.de (murzim.suse.de [10.160.4.192]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 54F10A3B84; Thu, 22 Jul 2021 06:38:21 +0000 (UTC) Date: Thu, 22 Jul 2021 08:38:21 +0200 (CEST) From: Richard Biener To: "Liu, Hongtao" cc: Uros Bizjak , Hongtao Liu , "gcc-patches@gcc.gnu.org" , "H. J. Lu" Subject: RE: [PATCH] Support logic shift left/right for avx512 mask type. In-Reply-To: Message-ID: References: <20210720123314.79588-1-hongtao.liu@intel.com> User-Agent: Alpine 2.21 (LSU 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Jul 2021 06:38:23 -0000 On Thu, 22 Jul 2021, Liu, Hongtao wrote: > > > >-----Original Message----- > >From: Uros Bizjak > >Sent: Wednesday, July 21, 2021 4:23 PM > >To: Hongtao Liu > >Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org; H. J. Lu > >; Richard Biener > >Subject: Re: [PATCH] Support logic shift left/right for avx512 mask type. > > > >On Wed, Jul 21, 2021 at 5:05 AM Hongtao Liu wrote: > >> > >> On Tue, Jul 20, 2021 at 9:41 PM Uros Bizjak wrote: > >> > > >> > On Tue, Jul 20, 2021 at 2:33 PM liuhongt wrote: > >> > > > >> > > Hi: > >> > > As mention in > >> > > https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575420.html > >> > > > >> > > ----cut start----- > >> > > > note for the lowpart we can just view-convert away the excess > >> > > > bits, fully re-using the mask. We generate surprisingly "good" code: > >> > > > > >> > > > kmovb %k1, %edi > >> > > > shrb $4, %dil > >> > > > kmovb %edi, %k2 > >> > > > > >> > > > besides the lack of using kshiftrb. I guess we're just lacking > >> > > > a mask register alternative for > >> > > Yes, we can do it similar as kor/kand/kxor. > >> > > ---cut end-------- > >> > > > >> > > Bootstrap and regtested on x86_64-linux-gnu{-m32,}. > >> > > Ok for trunk? > >> > > > >> > > gcc/ChangeLog: > >> > > > >> > > * config/i386/constraints.md (Wb): New constraint. > >> > > (Ww): Ditto. > >> > > * config/i386/i386.md (*ashlhi3_1): Extend to avx512 mask > >> > > shift. > >> > > (*ashlqi3_1): Ditto. > >> > > (*3_1): Ditto. > >> > > (*3_1): Ditto. > >> > > * config/i386/sse.md (k): New define_split after > >> > > it to convert generic shift pattern to mask shift ones. > >> > > > >> > > gcc/testsuite/ChangeLog: > >> > > > >> > > * gcc.target/i386/mask-shift.c: New test. > > > > > >+(define_insn "*lshr3_1" > >+ [(set (match_operand:SWI12 0 "nonimmediate_operand" "=m, ?k") > >+ (lshiftrt:SWI12 > >+ (match_operand:SWI12 1 "nonimmediate_operand" "0, k") > >+ (match_operand:QI 2 "nonmemory_operand" "c, "))) > >+ (clobber (reg:CC FLAGS_REG))] > >+ "ix86_binary_operator_ok (LSHIFTRT, mode, operands)" > > > >Also split this one to QImode and HImode to avoid conditions in isa attribute. > > > >OK with this change. > > > > Thanks for the review, here's the patch I'm check in. Works with my experimental patches, thanks! Richard.