Re: Re: [PATCH 1/1] Fix bit-position comparison

[Richard Biener <rguenther@suse.de>]

On Wed, 27 Jul 2022, juzhe.zhong@rivai.ai wrote:

> Thank you so much for the fast reply. Ok, it is true that I didn't think about it carefully. Can you help me with the following the issue?
> 
> For RVV (RISC-V 'V' Extension), we have full vector type 'vint8m1_t' (LMUL = 1) and fractional vector type 'vint8mf2_t' (LMUL = 1/2).

Can you explain in terms of GCCs generic vectors what vint8m1_t and
vint8mf2_t are?

> Because in the ISA, we don't have whole register load/store for fractional vector. I reference the LLVM implementation and I adjust BITSIZE of 
> fractional vector same as full vector (It will confuse GCC the bytesize of fractional vector and consider the spill size of a fractional vector is same as LMUL = 1) 
> so that I can use whole register load/store directly during the register spilling. (Even though it will enlarge the spill size). According to the machine_mode definition,
> The machine_mode PRECISION is calculate by component size which is different from BITSIZE
> 
> Now, here is the question. For array type: vint8mf2x4_t,  if I want to access vint8mf2x4_t[2], because the PRECISION and BITSIZE are different. Because bitops is calculated by
> bitsize and compare to precision in the codes that the patch mentioned. It will make a out-of-bounds access to small array.
> 
>  Can you help me with this? This is important for the following RVV upstream support. Thanks.

So you have that vint8mf2_t type and registers + instructions to operate 
on them but no way to load/store?  How do you implement

vint8mf2_t foo (vint8mf2_t *p)
{
  return *p;
}

?

> 
> 
> 
> 
> juzhe.zhong@rivai.ai
>  
> From: Richard Biener
> Date: 2022-07-27 14:46
> To: zhongjuzhe
> CC: gcc-patches; richard.earnshaw; jakub; kenner; jlaw; gnu; jason; davem; joseph; richard.sandiford; bernds_cb1; ian; wilson
> Subject: Re: [PATCH 1/1] Fix bit-position comparison
> On Wed, 27 Jul 2022, juzhe.zhong@rivai.ai wrote:
>  
> > From: zhongjuzhe <juzhe.zhong@rivai.ai>
> > 
> > gcc/ChangeLog:
> > 
> >         * expr.cc (expand_assignment): Change GET_MODE_PRECISION to GET_MODE_BITSIZE
> > 
> > ---
> >  gcc/expr.cc | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/gcc/expr.cc b/gcc/expr.cc
> > index 80bb1b8a4c5..ac2b3c07df6 100644
> > --- a/gcc/expr.cc
> > +++ b/gcc/expr.cc
> > @@ -5574,7 +5574,7 @@ expand_assignment (tree to, tree from, bool nontemporal)
> >  code contains an out-of-bounds access to a small array.  */
> >        if (!MEM_P (to_rtx)
> >    && GET_MODE (to_rtx) != BLKmode
> > -   && known_ge (bitpos, GET_MODE_PRECISION (GET_MODE (to_rtx))))
> > +   && known_ge (bitpos, GET_MODE_BITSIZE (GET_MODE (to_rtx))))
>  
> I think this has the chance to go wrong with regard to endianess.
> Consider to_rtx with 32bit mode size but 12bit mode precision.  bitpos
> is relative to the start of to_rtx as if it were in memory and bitsize
> determines the contiguous region affected.  But since we are actually
> storing into a non-memory endianess comes into play.
>  
> So no, I don't think the patch is correct, it would be way more
> complicated to get the desired improvement.
>  
> Richard.
>  
> >  {
> >    expand_normal (from);
> >    result = NULL;
> > 
>  
> 

-- 
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)