From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by sourceware.org (Postfix) with ESMTPS id 0DDDE385841D for ; Thu, 28 Jul 2022 07:45:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0DDDE385841D Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id 4D3C1337D6; Thu, 28 Jul 2022 07:45:27 +0000 (UTC) Received: from wotan.suse.de (wotan.suse.de [10.160.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id DC3F82C141; Thu, 28 Jul 2022 07:45:21 +0000 (UTC) Date: Thu, 28 Jul 2022 07:45:27 +0000 (UTC) From: Richard Biener To: jiawei cc: gcc-patches@gcc.gnu.org, jakub@redhat.com, palmer@rivosinc.com, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn Subject: Re: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works In-Reply-To: <20220728032544.2571608-1-jiawei@iscas.ac.cn> Message-ID: References: <20220728032544.2571608-1-jiawei@iscas.ac.cn> User-Agent: Alpine 2.22 (LSU 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jul 2022 07:45:29 -0000 On Thu, 28 Jul 2022, jiawei wrote: > This patch adds the additional options on RISC-V target. > "-fprefetch-loop-arrays" option needs enable prefetch instruction, > for RISC-V that contained in "zicbop" extension. > Use "-march" with "zicbop" will enable this feature. OK. Note -fprefetch-loop-arrays is just required to trigger an ICE, do you see a diagnostic when prefetching is not supported? Maybe simply adding -w is better then. > gcc/testsuite/ChangeLog: > > * gcc.dg/pr106397.c: New dg-additional-options for RISC-V. > > --- > gcc/testsuite/gcc.dg/pr106397.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c > index 2bc17f8cf80..19274fa8771 100644 > --- a/gcc/testsuite/gcc.dg/pr106397.c > +++ b/gcc/testsuite/gcc.dg/pr106397.c > @@ -1,6 +1,8 @@ > /* { dg-do compile } */ > /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */ > /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ > +/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */ > +/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */ > > int > bar (void) > -- Richard Biener SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)