From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by sourceware.org (Postfix) with ESMTPS id 64FA4385C8B0 for ; Fri, 30 Sep 2022 11:52:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 64FA4385C8B0 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out2.suse.de (Postfix) with ESMTP id 34EA61F8D3; Fri, 30 Sep 2022 11:52:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1664538763; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/OSPwFo+Qr0Y59+9gzeiw4VTg7AWTRRr1grcsARuCG4=; b=ZrWwKrMgZbbSUd6lp5euiqTaXw5OghTrlDwgQN2XnR3Mh8Rxs/pa6jfpEAuLqWvYQbJHD6 XbC5Lhchd5ijBBMOjesRsUJp/asOiOPjvMM5FIuYy86Lx80nal7syJxb0BiVHwPyoqGTq8 dUmpbcpbqLi7tOG2cWL4QrmzKPWXkgo= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1664538763; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/OSPwFo+Qr0Y59+9gzeiw4VTg7AWTRRr1grcsARuCG4=; b=jQlkkSkLbcVc9aNMyL9d6IPotWpo4I0zY6efHaN+oV6wKY05ScJtDSdFrY8coKnHOXwE7u lKbnWSnhMHaIpxDw== Received: from wotan.suse.de (wotan.suse.de [10.160.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 2C1012C161; Fri, 30 Sep 2022 11:52:43 +0000 (UTC) Date: Fri, 30 Sep 2022 11:52:42 +0000 (UTC) From: Richard Biener To: Tamar Christina cc: Richard Sandiford , Tamar Christina via Gcc-patches , nd , Jeff Law Subject: RE: [PATCH 1/2]middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type to backend In-Reply-To: Message-ID: References: <8873DC9F-F868-458D-9AD6-90DDC5465057@suse.de> User-Agent: Alpine 2.22 (LSU 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 30 Sep 2022, Tamar Christina wrote: > > -----Original Message----- > > From: Richard Biener > > Sent: Friday, September 30, 2022 11:17 AM > > To: Tamar Christina > > Cc: Richard Sandiford ; Tamar Christina via > > Gcc-patches ; nd ; Jeff Law > > > > Subject: RE: [PATCH 1/2]middle-end: RFC: On expansion of conditional > > branches, give hint if argument is a truth type to backend > > > > On Fri, 30 Sep 2022, Tamar Christina wrote: > > > > > > > > > > > > -----Original Message----- > > > > From: Richard Sandiford > > > > Sent: Friday, September 30, 2022 9:49 AM > > > > To: Tamar Christina > > > > Cc: Richard Biener ; Tamar Christina via > > > > Gcc-patches ; nd ; Jeff Law > > > > > > > > Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of conditional > > > > branches, give hint if argument is a truth type to backend > > > > > > > > Tamar Christina writes: > > > > >> -----Original Message----- > > > > >> From: Richard Sandiford > > > > >> Sent: Friday, September 30, 2022 9:29 AM > > > > >> To: Tamar Christina > > > > >> Cc: Richard Biener ; Tamar Christina via > > > > >> Gcc-patches ; nd ; Jeff > > Law > > > > >> > > > > >> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of > > > > >> conditional branches, give hint if argument is a truth type to > > > > >> backend > > > > >> > > > > >> Tamar Christina writes: > > > > >> >> -----Original Message----- > > > > >> >> From: Gcc-patches > > > >> >> bounces+tamar.christina=arm.com@gcc.gnu.org> On Behalf Of > > > > Richard > > > > >> >> Biener via Gcc-patches > > > > >> >> Sent: Thursday, September 29, 2022 12:09 PM > > > > >> >> To: Tamar Christina via Gcc-patches > > > > >> >> Cc: Richard Sandiford ; nd > > > > > > > > >> >> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of > > > > >> >> conditional branches, give hint if argument is a truth type to > > > > >> >> backend > > > > >> >> > > > > >> >> > > > > >> >> > > > > >> >> > Am 29.09.2022 um 12:23 schrieb Tamar Christina via > > > > >> >> > Gcc-patches > > > > >> >> > > > > >> >> patches@gcc.gnu.org>: > > > > >> >> > > > > > >> >> > > > > > >> >> >> > > > > >> >> >> -----Original Message----- > > > > >> >> >> From: Richard Biener > > > > >> >> >> Sent: Thursday, September 29, 2022 10:41 AM > > > > >> >> >> To: Richard Sandiford > > > > >> >> >> Cc: Jeff Law ; Tamar Christina > > > > >> >> >> ; gcc-patches@gcc.gnu.org; nd > > > > >> >> > > > > >> >> >> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of > > > > >> >> >> conditional branches, give hint if argument is a truth type > > > > >> >> >> to backend > > > > >> >> >> > > > > >> >> >>> On Thu, 29 Sep 2022, Richard Sandiford wrote: > > > > >> >> >>> > > > > >> >> >>> Jeff Law writes: > > > > >> >> >>>> On 9/28/22 09:04, Richard Sandiford wrote: > > > > >> >> >>>>> Tamar Christina writes: > > > > >> >> >>>>>>> Maybe the target could use (subreg:SI (reg:BI ...)) as > > > > argument. > > > > >> >> Heh. > > > > >> >> >>>>>> But then I'd still need to change the expansion code. I > > > > >> >> >>>>>> suppose this could prevent the issue with changes to > > > > >> >> >>>>>> code on > > > > >> other targets. > > > > >> >> >>>>>> > > > > >> >> >>>>>>>>> We have undocumented addcc, negcc, etc. patterns, > > > > should > > > > >> we > > > > >> >> >>>>>>>>> have aandcc > > > > >> >> >>>>>> pattern for this indicating support for andcc + jump as > > > > >> >> >>>>>> opposedto > > > > >> >> >> cmpcc + jump? > > > > >> >> >>>>>>>> This could work yeah. I didn't know these existed. > > > > >> >> >>>>>>> Ah, so they are conditional add, not add setting CC, > > > > >> >> >>>>>>> so andcc wouldn't be appropriate. > > > > >> >> >>>>>>> So I'm not sure how we'd handle such situation - maybe > > > > >> >> >>>>>>> looking at REG_DECL and recognizing a _Bool PARM_DECL > > > > >> >> >>>>>>> is > > > > OK? > > > > >> >> >>>>>> I have a slight suspicion that Richard Sandiford would > > > > >> >> >>>>>> likely reject this though.. > > > > >> >> >>>>> Good guess :-P We shouldn't rely on something like that > > > > >> >> >>>>> for > > > > >> >> >> correctness. > > > > >> >> >>>>> > > > > >> >> >>>>> Would it help if we promoted the test-and-branch > > > > >> >> >>>>> instructions to optabs, alongside cbranch? The jump > > > > >> >> >>>>> expanders could then target it > > > > >> >> >> directly. > > > > >> >> >>>>> > > > > >> >> >>>>> IMO that'd be a reasonable thing to do if it does help. > > > > >> >> >>>>> It's a relatively common operation, especially on CISCy > > targets. > > > > >> >> >>>> > > > > >> >> >>>> But don't we represent these single bit tests using > > > > >> >> >>>> zero_extract as the condition of the branch? I guess if > > > > >> >> >>>> we can generate them directly rather than waiting for > > > > >> >> >>>> combine to deduce that we're dealing with a single bit > > > > >> >> >>>> test and constructing the zero_extract form would be an > > > > >> >> >>>> improvement and might help aarch at the same > > > > >> time. > > > > >> >> >>> > > > > >> >> >>> Do you mean that the promote_mode stuff should use ext(z)v > > > > >> >> >>> rather than zero_extend to promote a bool, where available? > > > > >> >> >>> If so, I agree that might help. But it sounds like it > > > > >> >> >>> would have downsides > > > > >> too. > > > > >> >> >>> Currently a bool memory can be zero-extended on the fly > > > > >> >> >>> using a load, but if we used the zero_extract form > > > > >> >> >>> instead, we'd have to extract the bit after the load. And > > > > >> >> >>> (as an > > > > >> >> >>> alternative) choosing different behaviour based on whether > > > > >> >> >>> expand sees a REG or a MEM sounds like it could still > > > > >> >> >>> cause problems, since REGs could be replaced by MEMs (or > > > > >> >> >>> vice versa) > > > > later in the RTL passes. > > > > >> >> >>> > > > > >> >> >>> ISTM that the original patch was inserting an extra > > > > >> >> >>> operation in the branch expansion in order to target a specific > > instruction. > > > > >> >> >>> Targeting the instruction in expand seems good, but IMO we > > > > >> >> >>> should do it directly, based on knowledge of whether the > > > > >> >> >>> instruction actually > > > > >> >> exists. > > > > >> >> >> > > > > >> >> >> Yes, I think a compare-and-branch pattern is the best fit here. > > > > >> >> >> Note on GIMPLE we'd rely on the fact this is a BOOLEAN_TYPE > > > > >> >> >> (so even 8 bit precision bools only have 1 and 0 as meaningful > > values). > > > > >> >> >> So the 'compare-' bit in compare-and-branch would be > > > > >> >> >> interpreting a BOOLEAN_TYPE, not so much a general compare. > > > > >> >> > > > > > >> >> > Oh, I was thinking of adding a constant argument > > > > >> >> > representing the precision that is relevant for the compare > > > > >> >> > in order to make this a bit more > > > > >> >> general/future proof. > > > > >> >> > > > > > >> >> > Are you thinking I should instead just make the optab > > > > >> >> > implicitly only work for 1-bit precision comparisons? > > > > >> >> > > > > >> >> What?s the optab you propose (cite also the documentation part)? > > > > >> > > > > > >> > tbranchmode5 > > > > >> > Conditional branch instruction combined with a bit test instruction. > > > > >> Operand 0 is a comparison operator. > > > > >> > Operand 1 and Operand 2 are the first and second operands of > > > > >> > the > > > > >> comparison, respectively. > > > > >> > Operand 3 is the number of low-order bits that are relevant > > > > >> > for the > > > > >> comparison. > > > > >> > Operand 4 is the code_label to jump to. > > > > >> > > > > >> For the TB instructions (and for other similar instructions that > > > > >> I've seen on other architectures) it would be more useful to have > > > > >> a single-bit test, with operand 4 specifying the bit position. > > > > >> Arguably it might then be better to have separate eq and ne > > > > >> optabs, to avoid the awkward doubling of the operands (operand 1 > > > > >> contains > > > > operands 2 and 3). > > > > >> > > > > >> I guess a more general way of achieving the same thing would be > > > > >> to make operand 4 in the optab above a mask rather than a bit count. > > > > >> But that might be overly general, if there are no known > > > > >> architectures that have such an instruction. > > > > > > > > > > One of the reasons I wanted a range rather than a single bit is > > > > > that I can the use this to generate cbz/cbnz early on as well. > > > > > > > > We already have the opportunity to do that via cbranch4. > > > > But at the moment aarch64.md always forces the separate comparison > > > > instead. (Not sure why TBH. Does it enable more ifcvt > > > > opportunities?) > > > > > > > > If we change the body of cbranch4 to: > > > > > > > > if ((GET_CODE (operands[0]) != EQ && GET_CODE (operands[0]) != NE) > > > > || operands[2] != const0_rtx) > > > > { > > > > operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), > > > > operands[1], operands[2]); > > > > operands[2] = const0_rtx; > > > > } > > > > > > > > then we generate the cbz/cbnz directly. > > > > > > > > > > Ah ok, then if Richi agrees, bitpos it is then instead of bit count. > > > > Somehow I understood that cbranch<>4 is already fully capable of the > > optimization? > > > > On your earlier proposal I'd have commented that if it wouldn't make sense > > to instead have a CCmode setter instead of an expander with a branch label? > > That would be a bit test, like {sign,zero}_extract compared against zero which > > can then be combined with a branch? > > > > I missed that part, that could work too. > > > Of course if the ISA is really bit-test-and-branch then cbranch<>4 itself or a > > variant of it might be more useful. Maybe > > cbranchbi4 would be "abused" for this? > > The instruction is an actual bit-test-and-branch with any arbitrary bitpos. > Yes we can abuse cbranchbi4 for this, but then it also means we can't e.g. > use this to optimize a < 0 where a is a signed value. With the new optab > this would just be a bit-test-and-branch of the sign bit. > > But also I'm not entirely convinced that using `BImode` and assuming a single > bit is safe here. What happens if I compile my source with -std=c89? > > So I personally think the new optab makes more sense here. The CC setter would work too. > > I guess my question is, between you folks, which approach would you like. It seems that Richi > You'd like a CC setter. Richard do you have a preference of one over the other? My order of preference is a) an existing pattern, if possible b) something usable by N > 1 targets we know of, even if it requires some combine magic c) something that fits the actual ISA For b), x86 has BEXTR which performs a zero_extract from reg/mem and sets ZF when the result is zero. For a branch on sign bit there's easier ways, so it's probably not very useful for general compare and branch optimization and if (a & 0x30) is probably handled by combine(?). It also seems that if (a & 1) is handled for aarch64 already and it's just a lack of an optab that allows RTL expansion to expand if (bool) as if (bool & 1)? Richard. > Tamar > > > > > > Tamar > > > > > > > > > > Thanks, > > > > Richard > > > > > > > > > > > > > This would mean we could use my earlier patch that tried to drop > > > > > the QI/HI promotions without needing the any_extend additional > > > > > pass if we wanted to. > > > > > > > > > > We'd also no longer need to rely on seeing a paradoxical subreg for a > > tst. > > > > > > > > > > Tamar. > > > > > > > > > >> > > > > >> Thanks, > > > > >> Richard > > > > >> > > > > >> > Specifically this representation would allow us to emit all our > > > > >> > different conditional branching instructions without needing to > > > > >> > rely on combine. We have some cases that happen during > > > > >> > optimization that sometimes prevent the optimal sequence from > > > > >> > being generated. This > > > > >> would also solve that as we would expand to what we want to start > > with. > > > > >> > > > > > >> > Tamar. > > > > >> > > > > > >> >> > > > > >> >> > > > > > >> >> > Thanks, > > > > >> >> > Tamar > > > > >> >> > > > > > >> >> >> > > > > >> >> >> Richard. > > > > > > > -- > > Richard Biener > > SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 > > Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, > > Boudien Moerman; HRB 36809 (AG Nuernberg) > -- Richard Biener SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)