From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by sourceware.org (Postfix) with ESMTPS id 1BD353858C50 for ; Tue, 22 Nov 2022 11:08:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1BD353858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out2.suse.de (Postfix) with ESMTP id 57DF31F86B; Tue, 22 Nov 2022 11:08:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1669115280; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=OV1anIT8JKynqLdb3f4RjkBGE9Q47f2Z9/dPC9CUFuA=; b=YJKon7V6xeAjFFuWQu7sEfpHQ++YWvSCMQwTIeRdK72hDbGgL8XOiFeWG+8ibtLpESX/ri 1Zpq9XyPcKjklSMy4XsvSVvY0LAC0VFtgWQI0DPAAmPSSpM/k2mUdGLS0HewP4agM7pUDo taW9o4ASXxCg+cwJVknAyQLRICnFU/0= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1669115280; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=OV1anIT8JKynqLdb3f4RjkBGE9Q47f2Z9/dPC9CUFuA=; b=OHmXqAMa2ASIF9NBnyVWreCtMcqaT+XN5/eBA+nxMlPBaLDeE+LrPHOIgot4Pal1zFYPMB bY9OkLVwSgo2FKBA== Received: from wotan.suse.de (wotan.suse.de [10.160.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 4E9C92C142; Tue, 22 Nov 2022 11:08:00 +0000 (UTC) Date: Tue, 22 Nov 2022 11:08:00 +0000 (UTC) From: Richard Biener To: Richard Sandiford cc: Tamar Christina , Tamar Christina via Gcc-patches , Richard Biener , nd Subject: Re: [PATCH 1/8]middle-end: Recognize scalar reductions from bitfields and array_refs In-Reply-To: Message-ID: References: User-Agent: Alpine 2.22 (LSU 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 22 Nov 2022, Richard Sandiford wrote: > Tamar Christina writes: > >> -----Original Message----- > >> From: Richard Biener > >> Sent: Tuesday, November 22, 2022 10:59 AM > >> To: Richard Sandiford > >> Cc: Tamar Christina via Gcc-patches ; Tamar > >> Christina ; Richard Biener > >> ; nd > >> Subject: Re: [PATCH 1/8]middle-end: Recognize scalar reductions from > >> bitfields and array_refs > >> > >> On Tue, 22 Nov 2022, Richard Sandiford wrote: > >> > >> > Tamar Christina via Gcc-patches writes: > >> > >> So it's not easily possible the within current infrastructure. But > >> > >> it does look like ARM might eventually benefit from something like STV > >> on x86? > >> > >> > >> > > > >> > > I'm not sure. The problem with trying to do this in RTL is that > >> > > you'd have to be able to decide from two psuedos whether they come > >> > > from extracts that are sequential. When coming in from a hard > >> > > register that's easy yes. When coming in from a load, or any other > >> operation that produces psuedos that becomes harder. > >> > > >> > Yeah. > >> > > >> > Just in case anyone reading the above is tempted to implement STV for > >> > AArch64: I think it would set a bad precedent if we had a > >> > paste-&-adjust version of the x86 pass. AFAIK, the target > >> > capabilities and constraints are mostly modelled correctly using > >> > existing mechanisms, so I don't think there's anything particularly > >> > target-specific about the process of forcing things to be on the general or > >> SIMD/FP side. > >> > > >> > So if we did have an STV-ish thing for AArch64, I think it should be a > >> > target-independent pass that uses hooks and recog, even if the pass is > >> > initially enabled for AArch64 only. > >> > >> Agreed - maybe some of the x86 code can be leveraged, but of course the > >> cost modeling is the most difficult to get right - IIRC the x86 backend resorts > >> to backend specific tuning flags rather than trying to get rtx_cost or insn_cost > >> "correct" here. > >> > >> > (FWIW, on the patch itself, I tend to agree that this is really an SLP > >> > optimisation. If the vectoriser fails to see the benefit, or if it > >> > fails to handle more complex cases, then it would be good to try to > >> > fix that.) > >> > >> Also agreed - but costing is hard ;) > > > > I guess, I still disagree here but I've clearly been out-Richard. The problem is still > > that this is just basic codegen. I still don't think it requires -O2 to be usable. > > > > So I guess the only correct implementation is to use an STV-like patch. But given > > that this is already the second attempt, first RTL one was rejected by Richard, > > second GIMPLE one was rejected by Richi I'd like to get an agreement on this STV > > thing before I waste months more.. > > I don't think this in itself is a good motivation for STV. My comment > above was more about the idea of STV for AArch64 in general (since it > had been raised). > > Personally I still think the reduction should be generated in gimple. I agree, and the proper place to generate the reduction is in SLP. Richard.