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From: Richard Biener <rguenther@suse.de>
To: Richard Sandiford <richard.sandiford@arm.com>
Cc: Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org>,
	 Pan Li <incarnation.p.lee@outlook.com>,
	 "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
	 "pan2.li" <pan2.li@intel.com>,
	"Kito.cheng" <kito.cheng@sifive.com>
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Date: Wed, 1 Mar 2023 13:26:10 +0000 (UTC)	[thread overview]
Message-ID: <nycvar.YFH.7.77.849.2303011324560.27913@jbgna.fhfr.qr> (raw)
In-Reply-To: <mptmt4wmwwx.fsf@arm.com>

On Wed, 1 Mar 2023, Richard Sandiford wrote:

> Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> > I am not very familiar with the memory pattern, maybe juzhe can provide more information or correct me if anything is misleading.
> >
> > The different precision try to resolve the below bugs, the second vlm(with different size of load bytes compared to first one)
> > is eliminated because vbool8 and vbool16 have the same precision size, aka [8, 8].
> >
> > vbool8_t v2 = *(vbool8_t*)in;
> > vbool16_t v5 = *(vbool16_t*)in;
> > *(vbool16_t*)(out + 200) = v5;
> > *(vbool8_t*)(out + 100) = v2;
> >
> > addi    a4,a1,100
> > vsetvli a5,zero,e8,m1,ta,ma
> > addi    a1,a1,200
> > vlm.v   v24,0(a0)
> > vsm.v   v24,0(a4)
> > // Need one vsetvli and vlm.v for correctness here.
> > vsm.v   v24,0(a1)
> 
> But I think it's important to think about the patch as more than a way
> of fixing the bug above.  The aim has to be to describe the modes as they
> really are.
> 
> I don't think there's a way for GET_MODE_SIZE to be "conservatively wrong".
> A GET_MODE_SIZE that is too small would cause problems.  So would a
> GET_MODE_SIZE that is too big.
> 
> Like Richard says, I think the question comes down to the amount of padding.
> Is it the case that for 4+4X ([4,4]), the memory representation has 4 bits
> of padding for even X and 0 bits of padding for odd X?
> 
> I agree getting rid of GET_MODE_SIZE and representing everything in bits
> would avoid the problem at this point, but I think it would just be pushing
> the difficulty elsewhere.  E.g. stack layout will be "interesting" if we
> can't work in byte sizes.

I suppose the backend could ensure when it performs setvl, that we only
ever end up with the even or odd case and also restrict vectorization
that way?  So we could implement the working half and leave the not
working half never happening at runtime ...

Richard.

  reply	other threads:[~2023-03-01 13:26 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-16 15:11 incarnation.p.lee
     [not found] ` <9800822AA73B1E3D+5F679DFB-633A-446F-BB7F-59ADEEE67E50@rivai.ai>
2023-02-17  7:18   ` Li, Pan2
2023-02-17  7:36   ` Richard Biener
2023-02-17  8:39     ` Li, Pan2
2023-02-21  6:36       ` Li, Pan2
2023-02-21  8:28         ` Kito Cheng
2023-02-24  5:08           ` juzhe.zhong
2023-02-24  7:21             ` Li, Pan2
2023-02-27  3:43               ` Li, Pan2
2023-02-27 14:24 ` Richard Sandiford
2023-02-27 15:13   ` 盼 李
2023-02-28  2:27     ` Li, Pan2
2023-02-28  9:50       ` Richard Sandiford
2023-02-28  9:59         ` 盼 李
2023-02-28 14:07           ` Li, Pan2
2023-03-01 10:11             ` Richard Sandiford
2023-03-01 10:46               ` juzhe.zhong
2023-03-01 10:55                 ` 盼 李
2023-03-01 11:11                   ` Richard Sandiford
2023-03-01 11:26                     ` 盼 李
2023-03-01 11:53                     ` 盼 李
2023-03-01 12:03                       ` Richard Sandiford
2023-03-01 12:13                         ` juzhe.zhong
2023-03-01 12:27                           ` 盼 李
2023-03-01 12:33                         ` Richard Biener
2023-03-01 12:56                           ` Pan Li
2023-03-01 13:11                             ` Richard Biener
2023-03-01 13:19                             ` Richard Sandiford
2023-03-01 13:26                               ` Richard Biener [this message]
2023-03-01 13:50                               ` juzhe.zhong
2023-03-01 13:59                                 ` Richard Biener
2023-03-01 14:03                                   ` Richard Biener
2023-03-01 14:19                                     ` juzhe.zhong
2023-03-01 15:42                                       ` Li, Pan2
2023-03-01 15:46                                         ` Pan Li
2023-03-01 16:14                                         ` Richard Sandiford
2023-03-01 22:53                                           ` juzhe.zhong
2023-03-02  6:07                                             ` Li, Pan2
2023-03-02  8:25                                             ` Richard Biener
2023-03-02  8:37                                               ` juzhe.zhong
2023-03-02  9:39                                                 ` Richard Sandiford
2023-03-02 10:19                                                   ` juzhe.zhong
     [not found]                               ` <2023030121501634323743@rivai.ai>
2023-03-01 13:52                                 ` juzhe.zhong
2023-03-02  5:55 ` [PATCH v2] " pan2.li
2023-03-02  9:43   ` Richard Sandiford
2023-03-02 14:46     ` Li, Pan2
2023-03-02 17:54       ` Richard Sandiford
2023-03-03  2:34         ` Li, Pan2

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