From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by sourceware.org (Postfix) with ESMTPS id 4FE803858C83 for ; Wed, 1 Mar 2023 14:03:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4FE803858C83 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out2.suse.de (Postfix) with ESMTP id 7F29E1FE18; Wed, 1 Mar 2023 14:03:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1677679398; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=dxrXkaK/1UX/RHs8eX03TnIp/FGA9o/YGtRQjCTO8nE=; b=LpsOWajzGImRN6WK1MrFOatpSoZ/YSDm2utqGCusxfq08nuy1S1UDNlAIft/XcgbxVB/3c bZ+c5smhtWIpD8+/CIuJRnoEyBa8jWop69UNhUet/1njGdpvgNi2NB0y0Qz97tDnFgOb73 KK1rTBczEoq4s2UCPEA1YeGy1prTgrI= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1677679398; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=dxrXkaK/1UX/RHs8eX03TnIp/FGA9o/YGtRQjCTO8nE=; b=d2QKVjSmsv4RtcgSgNeNEpUIAXg9MEUmHAuyGmWxJEUxvB4+g9p9OW26M4uMghsy10mlSP G3XE8j3iCzkCDiBQ== Received: from wotan.suse.de (wotan.suse.de [10.160.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 6981C2C141; Wed, 1 Mar 2023 14:03:18 +0000 (UTC) Date: Wed, 1 Mar 2023 14:03:18 +0000 (UTC) From: Richard Biener To: juzhe.zhong@rivai.ai cc: "richard.sandiford" , gcc-patches , Pan Li , "pan2.li" , "kito.cheng" Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment In-Reply-To: Message-ID: References: User-Agent: Alpine 2.22 (LSU 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 1 Mar 2023, Richard Biener wrote: > On Wed, 1 Mar 2023, juzhe.zhong@rivai.ai wrote: > > > Let's me first introduce RVV load/store basics and stack allocation. > > For scalable vector memory allocation, we allocate memory according to machine vector-length. > > To get this CPU vector-length value (runtime invariant but compile time unknown), we have an instruction call csrr vlenb. > > For example, csrr a5,vlenb (store CPU a single register vector-length value (describe as bytesize) in a5 register). > > A single register size in bytes (GET_MODE_SIZE) is poly value (8,8) bytes. That means csrr a5,vlenb, a5 has the value of size poly (8,8) bytes. > > > > Now, our problem is that VNx1BI, VNx2BI, VNx4BI, VNx8BI has the same bytesize poly (1,1). So their storage consumes the same size. > > Meaning when we want to allocate a memory storge or stack for register spillings, we should first csrr a5, vlenb, then slli a5,a5,3 (means a5 = a5/8) > > Then, a5 has the bytesize value of poly (1,1). All VNx1BI, VNx2BI, VNx4BI, VNx8BI are doing the same process as I described above. They all consume > > the same memory storage size since we can't model them accurately according to precision or you bitsize. > > > > They consume the same storage (I am agree it's better to model them more accurately in case of memory storage comsuming). > > > > Well, even though they are consuming same size memory storage, I can make their memory accessing behavior (load/store) accurately by > > emiting the accurate RVV instruction for them according to RVV ISA. > > > > VNx1BI,VNx2BI, VNx4BI, VNx8BI are consuming same memory storage with size poly (1,1) > > The instruction for these modes as follows: > > VNx1BI: vsevl e8mf8 + vlm, loading 1/8 of poly (1,1) storage. > > VNx2BI: vsevl e8mf8 + vlm, loading 1/4 of poly (1,1) storage. > > VNx4BI: vsevl e8mf8 + vlm, loading 1/2 of poly (1,1) storage. > > VNx8BI: vsevl e8mf8 + vlm, loading 1 of poly (1,1) storage. > > > > So base on these, It's fine that we don't model VNx1BI,VNx2BI, VNx4BI, VNx8BI accurately according to precision or bitsize. > > This implementation is fine even though their memory storage is not accurate. > > > > However, the problem is that since they have the same bytesize, GCC will think they are the same and do some incorrect statement elimination: > > > > (Note: Load same memory base) > > load v0 VNx1BI from base0 > > load v1 VNx2BI from base0 > > load v2 VNx4BI from base0 > > load v3 VNx8BI from base0 > > > > store v0 base1 > > store v1 base2 > > store v2 base3 > > store v3 base4 > > > > This program sequence, in GCC, it will eliminate the last 3 load instructions. > > > > Then it will become: > > > > load v0 VNx1BI from base0 ===> vsetvl e8mf8 + vlm (only load 1/8 of poly size (1,1) memory data) > > > > store v0 base1 > > store v0 base2 > > store v0 base3 > > store v0 base4 > > > > This is what we want to fix. I think as long as we can have the way to differentiate VNx1BI,VNx2BI, VNx4BI, VNx8BI > > and GCC will not do th incorrect elimination for RVV. > > > > I think it can work fine even though these 4 modes consume inaccurate memory storage size > > but accurate data memory access load store behavior. > > So given the above I think that modeling the size as being the same > but with accurate precision would work. It's then only the size of the > padding in bytes we cannot represent with poly-int which should be fine. > > Correct? Btw, is storing a VNx1BI and then loading a VNx2BI from the same memory address well-defined? That is, how is the padding handled by the machine load/store instructions? Richard.