From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by sourceware.org (Postfix) with ESMTPS id B7A863858D1E for ; Wed, 19 Apr 2023 06:40:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B7A863858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out2.suse.de (Postfix) with ESMTP id D35021FD84; Wed, 19 Apr 2023 06:40:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1681886409; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wAYpHFqxz8NtJ7v/p+j4DnCZamIHiTFnHvYmjH2C1Ys=; b=Os4fU4xkDdXUmAN5qTs5cL6PrISQCKG157/mIEr/f4oa1s4V9k353ScW5aPhHn0j8deKSL 1N23QUTc/yvmkRl4OaZ+HjFA54GJ8ZXTgp8Wtr2hFjfzoUKzOzsPoaqZEqLJ5p8aSkYyhv hOE2KfOgreV03e2F95AeGFTbPvSoiu4= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1681886409; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wAYpHFqxz8NtJ7v/p+j4DnCZamIHiTFnHvYmjH2C1Ys=; b=EhfFTp82pzHsL6kDbCzgnklqpGExbF6XBBfNk+kFbjXFykGtDxAkUTyGzkVYPmtHuxm5+I pTFNBtGPwdBANHCg== Received: from wotan.suse.de (wotan.suse.de [10.160.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 8CC7B2C141; Wed, 19 Apr 2023 06:40:09 +0000 (UTC) Date: Wed, 19 Apr 2023 06:40:09 +0000 (UTC) From: Richard Biener To: pan2.li@intel.com cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com, richard.sandiford@arm.com, yanzhang.wang@intel.com Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization In-Reply-To: <20230418090855.3012513-1-pan2.li@intel.com> Message-ID: References: <20230417145025.2291874-1-pan2.li@intel.com> <20230418090855.3012513-1-pan2.li@intel.com> User-Agent: Alpine 2.22 (LSU 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 18 Apr 2023, pan2.li@intel.com wrote: > From: Pan Li > > This patch add the optimization for the vector IOR(V1, NOT V1). Assume > we have below sample code. > > vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) > { > return __riscv_vmorn_mm_b32(v1, v1, vl); > } > > Before this patch: > vsetvli a5,zero,e8,mf4,ta,ma > vlm.v v24,0(a1) > vsetvli zero,a2,e8,mf4,ta,ma > vmorn.mm v24,v24,v24 > vsetvli a5,zero,e8,mf4,ta,ma > vsm.v v24,0(a0) > ret > > After this patch: > vsetvli zero,a2,e8,mf4,ta,ma > vmset.m v24 > vsetvli a5,zero,e8,mf4,ta,ma > vsm.v v24,0(a0) > ret > > Or in RTL's perspective, > from: > (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 ]))) > to: > (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ]) > > The similar optimization like VMANDN has enabled already. There should > be no difference execpt the operator when compare the VMORN and VMANDN > for such kind of optimization. The patch allows the VECTOR_BOOL IOR(V1, NOT V1) > simplification besides the existing SCALAR_INT mode. > > gcc/ChangeLog: > > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): This needs some text > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Likewise. OK with that fixed. > * gcc.target/riscv/simplify_ior_optimization.c: New test. > > Signed-off-by: Pan Li > --- > gcc/simplify-rtx.cc | 4 +- > .../riscv/rvv/base/mask_insn_shortcut.c | 3 +- > .../riscv/simplify_ior_optimization.c | 50 +++++++++++++++++++ > 3 files changed, 53 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > index ee75079917f..3bc9b2f55ea 100644 > --- a/gcc/simplify-rtx.cc > +++ b/gcc/simplify-rtx.cc > @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, > if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1)) > || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0))) > && ! side_effects_p (op0) > - && SCALAR_INT_MODE_P (mode)) > - return constm1_rtx; > + && GET_MODE_CLASS (mode) != MODE_CC) > + return CONSTM1_RTX (mode); > > /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ > if (CONST_INT_P (op1) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > index 83cc4a1b5a5..57d0241675a 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > @@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) { > /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ > /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ > /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ > -/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ > /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ > /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ > -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ > +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */ > /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ > /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > new file mode 100644 > index 00000000000..ec3bd0baf03 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > @@ -0,0 +1,50 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */ > + > +#include > + > +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) > +{ > + return a | ~a; > +} > + > +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a) > +{ > + return a | ~a; > +} > + > +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a) > +{ > + return a | ~a; > +} > + > +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a) > +{ > + return a | ~a; > +} > + > +int8_t test_simplify_ior_scalar_case_4 (int8_t a) > +{ > + return a | ~a; > +} > + > +int16_t test_simplify_ior_scalar_case_5 (int16_t a) > +{ > + return a | ~a; > +} > + > +int32_t test_simplify_ior_scalar_case_6 (int32_t a) > +{ > + return a | ~a; > +} > + > +int64_t test_simplify_ior_scalar_case_7 (int64_t a) > +{ > + return a | ~a; > +} > + > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */ > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */ > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */ > +/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */ > +/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */ > -- Richard Biener SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)