* [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
@ 2023-10-13 5:45 Juzhe-Zhong
2023-10-13 6:01 ` Kito Cheng
2023-10-13 11:59 ` Richard Biener
0 siblings, 2 replies; 4+ messages in thread
From: Juzhe-Zhong @ 2023-10-13 5:45 UTC (permalink / raw)
To: gcc-patches; +Cc: jeffreyalaw, rguenther, Juzhe-Zhong
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
/* Disable for SVE because for long or variable-length vectors we don't
get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
because there we can vectorize the epilogue using mixed vector sizes.
- Likewise for AMD GCN. */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
+ Likewise for AMD GCN and RVV. */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
2023-10-13 5:45 [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Juzhe-Zhong
@ 2023-10-13 6:01 ` Kito Cheng
2023-10-13 6:04 ` juzhe.zhong
2023-10-13 11:59 ` Richard Biener
1 sibling, 1 reply; 4+ messages in thread
From: Kito Cheng @ 2023-10-13 6:01 UTC (permalink / raw)
To: Juzhe-Zhong; +Cc: GCC Patches, Jeff Law, Richard Biener
[-- Attachment #1: Type: text/plain, Size: 1351 bytes --]
LGTM
Juzhe-Zhong <juzhe.zhong@rivai.ai> 於 2023年10月12日 週四 22:45 寫道:
> Like ARM SVE and GCN, add RVV.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
>
> ---
> gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> index b348526b62f..f63b42a271a 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
> /* Disable for SVE because for long or variable-length vectors we don't
> get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
> because there we can vectorize the epilogue using mixed vector sizes.
> - Likewise for AMD GCN. */
> -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { !
> amdgcn*-*-* } } } } } */
> + Likewise for AMD GCN and RVV. */
> +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { !
> amdgcn*-*-* } && { ! riscv_v } } } } } } */
> --
> 2.36.3
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
2023-10-13 6:01 ` Kito Cheng
@ 2023-10-13 6:04 ` juzhe.zhong
0 siblings, 0 replies; 4+ messages in thread
From: juzhe.zhong @ 2023-10-13 6:04 UTC (permalink / raw)
To: kito.cheng; +Cc: gcc-patches, jeffreyalaw, rguenther
[-- Attachment #1: Type: text/plain, Size: 1519 bytes --]
Thanks. Committed.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-10-13 14:01
To: Juzhe-Zhong
CC: GCC Patches; Jeff Law; Richard Biener
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
LGTM
Juzhe-Zhong <juzhe.zhong@rivai.ai> 於 2023年10月12日 週四 22:45 寫道:
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
/* Disable for SVE because for long or variable-length vectors we don't
get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
because there we can vectorize the epilogue using mixed vector sizes.
- Likewise for AMD GCN. */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
+ Likewise for AMD GCN and RVV. */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
2023-10-13 5:45 [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Juzhe-Zhong
2023-10-13 6:01 ` Kito Cheng
@ 2023-10-13 11:59 ` Richard Biener
1 sibling, 0 replies; 4+ messages in thread
From: Richard Biener @ 2023-10-13 11:59 UTC (permalink / raw)
To: Juzhe-Zhong; +Cc: gcc-patches, jeffreyalaw
On Fri, 13 Oct 2023, Juzhe-Zhong wrote:
> Like ARM SVE and GCN, add RVV.
Adding RVV when SVE or GCN is already there looks obvious to me, these
kind of changes are pre-approved. No need for all the noise.
Thanks,
Richard.
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
>
> ---
> gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> index b348526b62f..f63b42a271a 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
> /* Disable for SVE because for long or variable-length vectors we don't
> get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
> because there we can vectorize the epilogue using mixed vector sizes.
> - Likewise for AMD GCN. */
> -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */
> + Likewise for AMD GCN and RVV. */
> +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH,
Frankenstrasse 146, 90461 Nuernberg, Germany;
GF: Ivo Totev, Andrew McDonald, Werner Knoblich; (HRB 36809, AG Nuernberg)
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2023-10-13 5:45 [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Juzhe-Zhong
2023-10-13 6:01 ` Kito Cheng
2023-10-13 6:04 ` juzhe.zhong
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