Re: [PATCH] [testsuite] [ppc] expect vectorization in gen-vect-11c.c

[Alexandre Oliva <oliva@adacore.com>]

Hello, Kewen,

On Mar 27, 2023, "Kewen.Lin" <linkw@linux.ibm.com> wrote:

> on 2023/3/25 16:35, Alexandre Oliva wrote:

>> The first loop in main gets stores "vectorized" on powerpc into
>> full-word stores, even without any vector instruction support, so the
>> test's expectation of no loop vectorization is not met.

> I think this test issue has been gone since r13-5771-gdc87e1391c55c6.

That patch has been backported to gcc-12 as r12-9258-g21e7145aaf582c.

> Could you have a double check?

I confirm I observe the problem with gcc-12 targeting ppc64-vx7r2,
containing the backported patch, and that the loop is vectorized,
failing the test.


It's unfortunately not viable for me to test GCC trunk with vxworks, so
my testing with it is limited to earlier GCC versions, that we (AdaCore)
have already ported or are in the process of porting.  I make up for
that by testing trunk with other target variants, to the best of my
abilities, to avoid regressions, but sometimes I just can't tell whether
my baseline for regression testing doesn't contain a failure because
there's another fix, or because it just doesn't fail on that target
variant.


In this case, the comments in the patch you mentioned don't seem to
match the situation at hand: the SImode stores vectorized into V2SImode
(DImode) seem profitable and are *not* split by vector lowering.

-- 
Alexandre Oliva, happy hacker                https://FSFLA.org/blogs/lxo/
   Free Software Activist                       GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about <https://stallmansupport.org>