From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) by sourceware.org (Postfix) with ESMTPS id 026B83858C39 for ; Thu, 25 May 2023 13:55:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 026B83858C39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=adacore.com Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-38eda4ef362so992470b6e.2 for ; Thu, 25 May 2023 06:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore.com; s=google; t=1685022955; x=1687614955; h=mime-version:user-agent:message-id:in-reply-to:date:errors-to :references:organization:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vucXB1Ia5psBT8oDcIaX6lLEJGINSaAHOhCkOb3Jk6s=; b=XGx5SHTXXqJkaicdzUn/Dv0l/WLDR6MmhyPbL2xWXYXF8OlF5zowKo5RIFOTW27AkO 4uExDspLquThnOVJLICOuyHPtrSu9BmsMKsM64NynNXvln4yM27gzg5kDKZjOpxg0dez qM6WWGLn2eqmKOExS3I0ELUtdkRsa+seg1Foh2NaRpTC3HyPKTbSYFpncxK4ddIeSLkO NCSJZS+naS/gXjuwfgzShUFYbu/DleyDLo0N9Frbiu+NX0eyeDvmGeGmV3woTSLq9Eav nX3af0cCupVT3VtfnDjEvrPxmWf0aDsrM04hLCtsMT4P/Ck/cmkbaQcrwZGkvEBxi9d4 bxlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685022955; x=1687614955; h=mime-version:user-agent:message-id:in-reply-to:date:errors-to :references:organization:subject:cc:to:from:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vucXB1Ia5psBT8oDcIaX6lLEJGINSaAHOhCkOb3Jk6s=; b=R1DuLkRXmomUe7dDjDLfL8QVVD8m1HMYcU0Kw0LPAp0Giq7tyfGv6UOo3l5GasAJZw Eqi8k4eZ7TamK9Q0KJjnZKBd2GoqOoJegZ3wJh5OgivCuu2q07uPZ3VishbFXdXlsvDK HJYKkx073xl9DeFukLzqS0Zf0ODSrhNGWRd7FDpTbw8lS14576Emk5w8fmzRmxOll/sf uUzxmf13UM3cmpVBL7ir9P/avAoN0WDFimEQljxvhvwtQSIq9epwjnSWAB7R63AaIyLF UpcWfqH71sYkRAhH53rmXMmh8YU7VIXIlZDrkZU80HR/Q+Dxf+zQYsNIP5QDQUeIe9UT xz9A== X-Gm-Message-State: AC+VfDy+Lq/D4KoWBGgbMO5CNer+sOFrrRpI/BB4PT5tplKHzkO9iMmo QY2XBeLzQPliUZjeXR+KhUR0jw== X-Google-Smtp-Source: ACHHUZ494umDkvFEqbeilUbBRnWofVqqw+declWSBieZhfbeIMLHCtyOuRxUk2Sp1AA0puMDGLrCMw== X-Received: by 2002:a05:6808:41:b0:398:4870:d2ed with SMTP id v1-20020a056808004100b003984870d2edmr3095932oic.13.1685022954093; Thu, 25 May 2023 06:55:54 -0700 (PDT) Received: from free.home ([2804:7f1:2080:6383:46d9:ede8:ee97:8cc0]) by smtp.gmail.com with ESMTPSA id s66-20020acaa945000000b003874e6dfeefsm549541oie.37.2023.05.25.06.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 06:55:53 -0700 (PDT) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 34PDtbPd3680968 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Thu, 25 May 2023 10:55:39 -0300 From: Alexandre Oliva To: Segher Boessenkool Cc: "Kewen.Lin" , Rainer Orth , Mike Stump , David Edelsohn , Kewen Lin , gcc-patches@gcc.gnu.org Subject: Re: [PATCH] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract* Organization: Free thinker, does not speak for AdaCore References: <0737fbfc-726c-ffca-5f36-d6b3f0decfec@linux.ibm.com> <20230525112200.GJ19790@gate.crashing.org> Errors-To: aoliva@lxoliva.fsfla.org Date: Thu, 25 May 2023 10:55:37 -0300 In-Reply-To: <20230525112200.GJ19790@gate.crashing.org> (Segher Boessenkool's message of "Thu, 25 May 2023 06:22:00 -0500") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On May 25, 2023, Segher Boessenkool wrote: > Fwiw, updating the insn counts blindly like this ... is a claim that carries a wildly incorrect and insulting underlying assumption: I've actually identified the corresponding change to the lp64 tests, compared the effects of the codegen changes, and concluded the tests needed this changing for ilp32 to keep on testing for the same thing after code changes brought about by changes that AFAICT had been well understood when making the lp64 adjustments. > If it is not possible to keep these tests up-to-date easily The counts have been stable for a couple of release cycles already. The change that caused the codegen differences is identified and understood; the PR confirmed my findings, naming the root cause and the incomplete testsuite adjustment. I suspect there may also be ABI-related assumptions implied by the 'add' counts, but I don't know enough about all the ppc variants to be sure. Now, if your implied claim is correct that counting 'add/addi' instructions in these tests is fragile, dropping the checks for those would probably be best. But if ppc maintainers seem to have different opinions as to how to deal with the fallout of that one-time codegen change, it would be foolish for me to get pulled into the cross fire. Here's the patch that corrects the long-broken counts, with the requested adjustments, retested with ppc- and ppc64-vx7r2. Ok? [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract* Codegen changes caused add instruction count mismatches on ppc-*-linux-gnu and other 32-bit ppc targets. At some point the expected counts were adjusted for lp64, but ilp32 differences remained, and published test results confirm it. for gcc/testsuite/ChangeLog PR testsuite/101169 * gcc.target/powerpc/fold-vec-extract-char.p7.c: Adjust addi counts for ilp32. * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. --- .../gcc.target/powerpc/fold-vec-extract-char.p7.c | 3 ++- .../powerpc/fold-vec-extract-double.p7.c | 3 +-- .../gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +-- .../gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +- .../gcc.target/powerpc/fold-vec-extract-int.p7.c | 3 +-- .../gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +- .../gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +-- .../gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +- 8 files changed, 9 insertions(+), 12 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c index 29a8aa84db282..c6647431d09c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c @@ -11,7 +11,8 @@ /* one extsb (extend sign-bit) instruction generated for each test against unsigned types */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 9 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target { ilp32 } } } } */ /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ /* -m32 target uses rlwinm in place of rldicl. */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c index 3cae644b90b71..cbf6cffbeba17 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c @@ -13,8 +13,7 @@ /* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */ /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ /* -m32 target has an 'add' in place of one of the 'addi'. */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */ /* -m32 target has a rlwinm in place of a rldic . */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c index 59a4979457dcb..c9abb6c1f352c 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c @@ -12,8 +12,7 @@ /* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ /* -m32 as an add in place of an addi. */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */ /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */ /* -m32 uses rlwinm in place of rldic */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c index 4b1d75ee26d0f..68eeeede4b307 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c @@ -26,7 +26,7 @@ /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c index 3729a1646e9c9..418762e3948a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c @@ -10,8 +10,7 @@ // P7 variables: li, addi, stxvw4x, lwa/lwz /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c index 75eaf25943b70..d1e3b62373f80 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c @@ -30,7 +30,7 @@ /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c index a495d9f3928fa..46e943faa6a41 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c @@ -10,8 +10,7 @@ // P7 (be) constants: li, addi, stxvw4x, lha/lhz /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */ /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */ /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c index 0ddecb4e4b55d..00685aca1367b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c @@ -32,7 +32,7 @@ /* add and rlwinm instructions only on the variable tests. */ /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */ -- Alexandre Oliva, happy hacker https://FSFLA.org/blogs/lxo/ Free Software Activist GNU Toolchain Engineer Disinformation flourishes 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