From: Tamar Christina <tamar.christina@arm.com>
To: gcc-patches@gcc.gnu.org
Cc: nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com,
Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com
Subject: [PATCH]AArch64 Fix ILP32 tbranch
Date: Tue, 13 Dec 2022 17:14:27 +0000 [thread overview]
Message-ID: <patch-16700-tamar@arm.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 1242 bytes --]
Hi All,
the baremetal builds are currently broken because the shift ends up in the wrong
representation if the mode is SImode and the shift amount if 31. To fix this
create the rtx constant with an explicit mode so the backend passes know which
representation it needs to take.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Build aarch64-none-elf with ILP32 multilib and no issues
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64.md (tbranch_<code><mode>3): Use gen_int_mode.
--- inline copy of patch --
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d749c98eef63de4b92e589a167af823416f6a71d..6c27fb89e663d6ed845b41daf32476c2a58a169c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -957,7 +957,7 @@ (define_expand "tbranch_<code><mode>3"
{
rtx bitvalue = gen_reg_rtx (<ZEROM>mode);
rtx reg = gen_lowpart (<ZEROM>mode, operands[0]);
- rtx val = GEN_INT (1UL << UINTVAL (operands[1]));
+ rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode);
emit_insn (gen_and<zerom>3 (bitvalue, reg, val));
operands[1] = const0_rtx;
operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue,
--
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diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d749c98eef63de4b92e589a167af823416f6a71d..6c27fb89e663d6ed845b41daf32476c2a58a169c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -957,7 +957,7 @@ (define_expand "tbranch_<code><mode>3"
{
rtx bitvalue = gen_reg_rtx (<ZEROM>mode);
rtx reg = gen_lowpart (<ZEROM>mode, operands[0]);
- rtx val = GEN_INT (1UL << UINTVAL (operands[1]));
+ rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode);
emit_insn (gen_and<zerom>3 (bitvalue, reg, val));
operands[1] = const0_rtx;
operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue,
next reply other threads:[~2022-12-13 17:14 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-13 17:14 Tamar Christina [this message]
2022-12-13 17:15 ` Kyrylo Tkachov
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