From: "Jan Beulich" <JBeulich@novell.com>
To: <gcc-patches@gcc.gnu.org>
Subject: x86: fix for gcc.c-torture/execute/va-arg-25.c execution at -Os
Date: Thu, 08 Jul 2004 14:39:00 -0000 [thread overview]
Message-ID: <s0ed5ce3.080@emea1-mh.id2.novell.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 384 bytes --]
(resending with patch only in attachment because it got rejected by
sourceware's spam checker)
However, the newly added test gcc.c-torture/execute/va-arg-26.c once
again
fails (on systems supporting SSE2) and will continue to do so until the
collision
between -Os and the required alignment of SSE/SSE2 vector types has
been
fixed.
boostrapped and tested on i686-pc-linux-gnu.
Jan
[-- Attachment #2: gcc-mainline-x86-vector-va-arg.patch --]
[-- Type: application/octet-stream, Size: 4749 bytes --]
This fixes gcc.c-torture/execute/va-arg-25.c execution at -Os. However, the
newly added test gcc.c-torture/execute/va-arg-26.c once again fails (on
systems supporting SSE2) and will continue to do so until the collision
between -Os and the required alignment of SSE/SSE2 vector types has been
fixed.
2004-07-08 Jan Beulich <jbeulich@novell.com>
* config/i386/i386.c (init_cumulative_args): Set mmx/sse registers
available for use only when TARGET_MMX/_SSE is set, and check for
variable argument function if any register count is non-zero.
(function_arg): Correctly suppress repeated warnings for passing SSE
vectors are arguments without SSE enabled.
(ix86_function_arg_boundary): Without SSE enabled, the use of what
would be SSE register modes does no longer influence the alignment.
testsuite:
2004-07-08 Jan Beulich <jbeulich@novell.com>
* gcc.c-torture/execute/va-arg-26.[cx]: New (x86-specific)
test.
--- /home/jbeulich/src/gcc/mainline/2004-07-05.10.09/gcc/config/i386/i386.c 2004-07-02 15:20:42.000000000 +0200
+++ 2004-07-05.10.09/gcc/config/i386/i386.c 2004-07-07 15:43:51.817899296 +0200
@@ -1917,8 +1917,10 @@
cum->nregs = ix86_function_regparm (fntype, fndecl);
else
cum->nregs = ix86_regparm;
- cum->sse_nregs = SSE_REGPARM_MAX;
- cum->mmx_nregs = MMX_REGPARM_MAX;
+ if (TARGET_SSE)
+ cum->sse_nregs = SSE_REGPARM_MAX;
+ if (TARGET_MMX)
+ cum->mmx_nregs = MMX_REGPARM_MAX;
cum->warn_sse = true;
cum->warn_mmx = true;
cum->maybe_vaarg = false;
@@ -1937,9 +1939,9 @@
/* Determine if this function has variable arguments. This is
indicated by the last argument being 'void_type_mode' if there
are no variable arguments. If there are variable arguments, then
- we won't pass anything in registers */
+ we won't pass anything in registers in 32-bit mode. */
- if (cum->nregs || !TARGET_MMX || !TARGET_SSE)
+ if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
{
for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
param != 0; param = next_param)
@@ -2671,7 +2673,7 @@
case V2DFmode:
if (!type || !AGGREGATE_TYPE_P (type))
{
- if (!TARGET_SSE && !warnedmmx && cum->warn_sse)
+ if (!TARGET_SSE && !warnedsse && cum->warn_sse)
{
warnedsse = true;
warning ("SSE vector argument without SSE enabled "
@@ -2819,7 +2821,9 @@
The handling here differs from field_alignment. ICC aligns MMX
arguments to 4 byte boundaries, while structure fields are aligned
to 8 byte boundaries. */
- if (!type)
+ if (!TARGET_SSE)
+ align = PARM_BOUNDARY;
+ else if (!type)
{
if (!SSE_REG_MODE_P (mode))
align = PARM_BOUNDARY;
--- /home/jbeulich/src/gcc/mainline/2004-07-05.10.09/gcc/testsuite/gcc.c-torture/execute/va-arg-26.c 1970-01-01 01:00:00.000000000 +0100
+++ 2004-07-05.10.09/gcc/testsuite/gcc.c-torture/execute/va-arg-26.c 2004-06-15 09:37:03.000000000 +0200
@@ -0,0 +1,62 @@
+/* Varargs and vectors! */
+
+#include <stdarg.h>
+
+#define vector __attribute__((vector_size(16)))
+
+const vector unsigned int v1 = {10,11,12,13};
+const vector unsigned int v2 = {20,21,22,23};
+
+void foo(int a, ...)
+{
+ va_list args;
+ vector unsigned int v;
+
+ va_start (args, a);
+ v = va_arg (args, vector unsigned int);
+ if (a != 1 || memcmp (&v, &v1, sizeof (v)) != 0)
+ abort ();
+ a = va_arg (args, int);
+ if (a != 2)
+ abort ();
+ v = va_arg (args, vector unsigned int);
+ if (memcmp (&v, &v2, sizeof (v)) != 0)
+ abort ();
+ va_end (args);
+}
+
+static void bail_if_no_sse (void)
+{
+ int fl1, fl2;
+
+ /* See if we can use cpuid. */
+ __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
+ "pushl %0; popfl; pushfl; popl %0; popfl"
+ : "=&r" (fl1), "=&r" (fl2)
+ : "i" (0x00200000));
+ if (((fl1 ^ fl2) & 0x00200000) == 0)
+ exit (0);
+
+ /* See if cpuid gives capabilities. */
+ __asm__ ("cpuid" : "=a" (fl1) : "0" (0) : "ebx", "ecx", "edx");
+ if (fl1 == 0)
+ exit (0);
+
+ /* See if capabilities include SSE (25th bit; 26 for SSE2). */
+ __asm__ ("cpuid" : "=a" (fl1), "=d" (fl2) : "0" (1) : "ebx", "ecx");
+#ifdef __OPTIMIZE_SIZE__
+ if ((fl2 & (1 << 25)) == 0)
+#else
+ if ((fl2 & (1 << 26)) == 0)
+#endif
+ exit (0);
+}
+
+int main(void)
+{
+ bail_if_no_sse ();
+
+ foo (1, (vector unsigned int){10,11,12,13}, 2,
+ (vector unsigned int){20,21,22,23});
+ return 0;
+}
--- /home/jbeulich/src/gcc/mainline/2004-07-05.10.09/gcc/testsuite/gcc.c-torture/execute/va-arg-26.x 1970-01-01 01:00:00.000000000 +0100
+++ 2004-07-05.10.09/gcc/testsuite/gcc.c-torture/execute/va-arg-26.x 2004-06-09 16:33:56.000000000 +0200
@@ -0,0 +1,5 @@
+if { [istarget "i?86-*-*"] } {
+ set additional_flags "-msse2"
+ return 0
+}
+return 1
next reply other threads:[~2004-07-08 13:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-07-08 14:39 Jan Beulich [this message]
2004-07-10 5:17 ` Richard Henderson
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