Re:Fw: [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup

["Lehua Ding" <lehua.ding@rivai.ai>]

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Committed to the trunk, thanks Richard and Juzhe.


1. bootstrap and regression are pass on i386 target (by Pan).
2. no new failed testcases on AArch64 target.


Best,
Lehua


------------------ Original ------------------
From:                                                                                                                        "Richard Sandiford"                                                                                    <gcc-patches@gcc.gnu.org&gt;;
Date:&nbsp;Mon, Jul 17, 2023 10:44 PM
To:&nbsp;"juzhe.zhong"<juzhe.zhong@rivai.ai&gt;;
Cc:&nbsp;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;;
Subject:&nbsp;Re: [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup



juzhe.zhong@rivai.ai writes:
&gt; From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai&gt;
&gt;
&gt; Hi, Richard.
&gt;
&gt; RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
&gt; There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
&gt;
&gt; When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE:
&gt; rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186
&gt;&nbsp; &nbsp; 13 | }
&gt;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; | ^
&gt; 0xf7a5b1 partial_subreg_p(machine_mode, machine_mode)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl.h:3186
&gt; 0x1407616 wider_subreg_mode(machine_mode, machine_mode)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl.h:3252
&gt; 0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677
&gt; 0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146
&gt; 0x2a2c142 rtl_ssa::function_info::simplify_phis()
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258
&gt; 0x2a2b3f0 rtl_ssa::function_info::function_info(function*)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51
&gt; 0x1cebab9 pass_vsetvl::init()
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578
&gt; 0x1cec150 pass_vsetvl::execute(function*)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
&gt;
&gt; The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97]
&gt; When the PHI input def comes from ENTRY BLOCK (index =0), the def-&gt;mode () = V32QImode.
&gt; But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes).
&gt; Then combine_modes report ICE.
&gt;
&gt; gcc/ChangeLog:
&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; * rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred.

OK if it passes testing.

Thanks,
Richard

&gt; ---
&gt;&nbsp; gcc/rtl-ssa/internals.inl | 3 +++
&gt;&nbsp; 1 file changed, 3 insertions(+)
&gt;
&gt; diff --git a/gcc/rtl-ssa/internals.inl b/gcc/rtl-ssa/internals.inl
&gt; index 0a61811289d..e49297c12b3 100644
&gt; --- a/gcc/rtl-ssa/internals.inl
&gt; +++ b/gcc/rtl-ssa/internals.inl
&gt; @@ -673,6 +673,9 @@ combine_modes (machine_mode mode1, machine_mode mode2)
&gt;&nbsp; &nbsp; if (mode2 == E_BLKmode)
&gt;&nbsp;&nbsp;&nbsp; &nbsp; return mode1;
&gt;&nbsp; 
&gt; +&nbsp; if (!ordered_p (GET_MODE_SIZE (mode1), GET_MODE_SIZE (mode2)))
&gt; +&nbsp; &nbsp; return BLKmode;
&gt; +
&gt;&nbsp; &nbsp; return wider_subreg_mode (mode1, mode2);
&gt;&nbsp; }