From: =?gb18030?B?1tO+09Xc?= <juzhe.zhong@rivai.ai>
To: =?gb18030?B?cGFuMi5saQ==?= <pan2.li@intel.com>,
=?gb18030?B?Z2NjLXBhdGNoZXM=?= <gcc-patches@gcc.gnu.org>
Cc: =?gb18030?B?a2l0by5jaGVuZw==?= <kito.cheng@gmail.com>,
=?gb18030?B?amVmZnJleWFsYXc=?= <jeffreyalaw@gmail.com>,
=?gb18030?B?cmRhcHAuZ2Nj?= <rdapp.gcc@gmail.com>,
=?gb18030?B?UGFuIExp?= <pan2.li@intel.com>
Subject: Re: [PATCH v1 4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
Date: Wed, 19 Jun 2024 21:20:45 +0800 [thread overview]
Message-ID: <tencent_57D6CB8C77320C8A55DE10D2@qq.com> (raw)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb18030", Size: 33383 bytes --]
lgtm
----------Reply to Message----------
On Wed, Jun 19, 2024 21:17 PM pan2.li<pan2.li@intel.com> wrote:
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 6:
#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= y ? 0 : x - y; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h | 16 ++++
.../rvv/autovec/binop/vec_sat_u_sub-21.c | 19 +++++
.../rvv/autovec/binop/vec_sat_u_sub-22.c | 20 +++++
.../rvv/autovec/binop/vec_sat_u_sub-23.c | 20 +++++
.../rvv/autovec/binop/vec_sat_u_sub-24.c | 20 +++++
.../rvv/autovec/binop/vec_sat_u_sub-run-21.c | 75 +++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_sub-run-22.c | 75 +++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_sub-run-23.c | 75 +++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_sub-run-24.c | 75 +++++++++++++++++++
9 files changed, 395 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index b25215c10cb..fd4d88e6f30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -206,6 +206,19 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
} \
}
+#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x <= y ? 0 : x - y; \
+ } \
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -221,4 +234,7 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
new file mode 100644
index 00000000000..9799a1eb0c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_uint8_t_fmt_6:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
+** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
new file mode 100644
index 00000000000..bb1eeb42cf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_uint16_t_fmt_6:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** ...
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
new file mode 100644
index 00000000000..642003cc118
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_uint32_t_fmt_6:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** ...
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
new file mode 100644
index 00000000000..9bc95295738
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_uint64_t_fmt_6:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c
new file mode 100644
index 00000000000..aec82f86376
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint8_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6
+
+DEF_VEC_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+0, 255, 255, 255,
+0, 255, 255, 255,
+0, 255, 255, 255,
+0, 255, 255, 255,
+ },
+ {
+1, 255, 254, 251,
+1, 255, 254, 251,
+1, 255, 254, 251,
+1, 255, 254, 251,
+ },
+ {
+0, 0, 1, 4,
+0, 0, 1, 4,
+0, 0, 1, 4,
+0, 0, 1, 4,
+ },
+ },
+ {
+ {
+0, 0, 1, 0,
+1, 2, 3, 0,
+1, 2, 3, 255,
+5, 254, 255, 9,
+ },
+ {
+0, 1, 0, 254,
+ 254, 254, 254, 255,
+ 255, 255, 0, 252,
+ 255, 255, 255, 1,
+ },
+ {
+0, 0, 1, 0,
+0, 0, 0, 0,
+0, 0, 3, 3,
+0, 0, 0, 8,
+ },
+ },
+};
+
+#include "vec_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c
new file mode 100644
index 00000000000..bd5c7d206b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint16_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6
+
+DEF_VEC_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ },
+ {
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ },
+ {
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ },
+ },
+ {
+ {
+ 0, 0, 1, 0,
+ 1, 2, 3, 0,
+ 1, 65535, 3, 65535,
+ 5, 65534, 65535, 9,
+ },
+ {
+ 0, 1, 1, 65534,
+ 65534, 65534, 1, 65535,
+ 0, 65535, 65535, 0,
+ 65535, 65535, 1, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 2, 0,
+ 1, 0, 0, 65535,
+ 0, 0, 65534, 7,
+ },
+ },
+};
+
+#include "vec_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c
new file mode 100644
index 00000000000..f5a1d6bd930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint32_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6
+
+DEF_VEC_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ {
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ },
+ {
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ },
+ },
+ {
+ {
+ 0, 0, 9, 0,
+ 1, 4294967295, 3, 0,
+ 1, 2, 3, 4,
+ 5, 4294967294, 4294967295, 4294967295,
+ },
+ {
+ 0, 1, 1, 4294967294,
+ 1, 2, 4294967294, 4294967295,
+ 1, 4294967295, 4294967295, 1,
+ 1, 4294967295, 4294967290, 9,
+ },
+ {
+ 0, 0, 8, 0,
+ 0, 4294967293, 0, 0,
+ 0, 0, 0, 3,
+ 4, 0, 5, 4294967286,
+ },
+ },
+};
+
+#include "vec_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c
new file mode 100644
index 00000000000..62c54a21e6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint64_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6
+
+DEF_VEC_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ }, /* arg_1 */
+ {
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
+ },
+ {
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u,
+ },
+ {
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u,
+ },
+ },
+ {
+ {
+ 0, 18446744073709551615u, 1, 0,
+ 1, 18446744073709551615u, 3, 0,
+ 1, 18446744073709551614u, 3, 4,
+ 5, 18446744073709551614u, 18446744073709551615u, 9,
+ },
+ {
+ 0, 1, 1, 18446744073709551614u,
+ 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1,
+ },
+ {
+ 0, 18446744073709551614u, 0, 0,
+ 0, 1, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 8,
+ },
+ },
+};
+
+#include "vec_sat_binary.h"
--
2.34.1
next reply other threads:[~2024-06-19 13:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 13:20 =?gb18030?B?1tO+09Xc?= [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-06-19 13:16 [PATCH v1 1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 pan2.li
2024-06-19 13:17 ` [PATCH v1 4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 pan2.li
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