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From: Richard Earnshaw <rearnsha@arm.com> To: nobody@gcc.gnu.org Cc: gcc-prs@gcc.gnu.org Subject: Re: libstdc++/3584: arm-specific atomic operations not atomic Date: Wed, 11 Jul 2001 11:06:00 -0000 [thread overview] Message-ID: <20010711180601.17556.qmail@sourceware.cygnus.com> (raw) The following reply was made to PR libstdc++/3584; it has been noted by GNATS. From: Richard Earnshaw <rearnsha@arm.com> To: Robin Farine <acnrf@dial.eunet.ch> Cc: Richard.Earnshaw@arm.com, robin.farine@terminus.org, gcc-gnats@gcc.gnu.org Subject: Re: libstdc++/3584: arm-specific atomic operations not atomic Date: Wed, 11 Jul 2001 19:04:22 +0100 > This certainly works correctly but it would introduce another problem. If > another thread already holds the lock, the current thread would just spin > hopelessly until the thread that holds the lock gets the CPU and releases > it. This could result into a dead-lock if the spinning thread has a higher > priority than the lock owner. > > With the swap instruction (in contrast to test-and-set ;-)), I think that such > routines implementations have to depend on the threading model to explicitly > release the CPU when they fail to get the lock. Something like: Correct. I was forgetting that the load-locked/store-conditional operations wouldn't suffer from this problem. That makes the sequence particularly nasty, especially when called from thumb code... :-( R.
next reply other threads:[~2001-07-11 11:06 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2001-07-11 11:06 Richard Earnshaw [this message] -- strict thread matches above, loose matches on Subject: below -- 2002-10-03 9:17 rearnsha 2002-05-31 18:09 pme 2001-07-12 7:26 Richard Earnshaw 2001-07-12 7:16 Robin Farine 2001-07-11 10:36 Robin Farine 2001-07-11 8:46 Richard Earnshaw 2001-07-06 2:56 robin.farine
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