other/8553: AltiVec vec_abs broken at -O0 with register keyword

[hartwood@crosslink.net]

>Number:         8553
>Category:       other
>Synopsis:       AltiVec vec_abs broken at -O0 with register keyword
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    unassigned
>State:          open
>Class:          wrong-code
>Submitter-Id:   net
>Arrival-Date:   Tue Nov 12 11:36:05 PST 2002
>Closed-Date:
>Last-Modified:
>Originator:     Rick Cellucci
>Release:        gcc version 3.3 20021104 (experimental)
>Organization:
>Environment:
Configured with: ../gcc3.3/configure --prefix=/usr/local/darwin --enable-altivec --enable-languages=c --with-cpu=7400 --target=powerpc-apple-darwin6.1
>Description:
With no optimization, specifying a register vector variable will stomp on the temporary registers used by the vec_abs function, which actually generates 3 vector instructions.
>How-To-Repeat:
void VecAbsIsBroken (short *image)
/* gcc3.3 broken at -O0, works at -O1 and above, remove register keyword to fix */
{
	short *p;
	register vector signed short v;
	
	p = image;
	v = vec_ld (0, p);
	v = vec_abs (v);
	
	printf ("%p %hd: ", p, *p);
	PrintShortVector (v); printf ("\n");
}
/*

_VecAbsIsBroken:
L_VecAbsIsBroken$stub: 
        mfspr r12,256
        stw r12,-12(r1)
        oris r12,r12,0xdfff
        ori r12,r12,61440
        mtspr 256,r12
        mflr r0
        stw r30,-8(r1)
        stw r31,-4(r1)
        stw r0,8(r1)
        stwu r1,-96(r1)
        mr r30,r1      
        bcl 20,31,L4$pb 
L4$pb:
        mflr r31      
        stw r3,120(r30)
        lwz r0,120(r30)
        stw r0,56(r30)
        li r11,0       
        lwz r9,56(r30)
        lvx v0,r11,r9
        addi r9,r30,64
        stvx v0,0,r9
        addi r9,r30,64
        lvx v1,0,r9             By loading v1 with the input to vec_abs, we doom it to fail
        
        vspltisb v1,0           v1 should NOT be used as a temporary register here
        vsubuhm v13,v1,v1       This just zeroed out v13, not good!
        vmaxsh v0,v1,v13        So we end up with 0s!
        
        addi r9,r30,64
        stvx v0,0,r9
*/
>Fix:
Workaround: Use higher optimization levels. Still, without optimization the code should be generated correctly.
>Release-Note:
>Audit-Trail:
>Unformatted: