From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31443 invoked by alias); 31 Jan 2003 15:25:26 -0000 Mailing-List: contact gcc-prs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-prs-owner@gcc.gnu.org Received: (qmail 31424 invoked by uid 48); 31 Jan 2003 15:25:26 -0000 Date: Fri, 31 Jan 2003 15:25:00 -0000 Message-ID: <20030131152526.31423.qmail@sources.redhat.com> To: gcc-bugs@gcc.gnu.org, gcc-prs@gcc.gnu.org, nobody@gcc.gnu.org, trauscher@loytec.com From: rearnsha@gcc.gnu.org Reply-To: rearnsha@gcc.gnu.org, gcc-bugs@gcc.gnu.org, gcc-prs@gcc.gnu.org, nobody@gcc.gnu.org, trauscher@loytec.com, gcc-gnats@gcc.gnu.org Subject: Re: target/8159: ARM/THUMB code uses sp as index register for automatic arrays X-SW-Source: 2003-01/txt/msg01762.txt.bz2 List-Id: Synopsis: ARM/THUMB code uses sp as index register for automatic arrays State-Changed-From-To: open->closed State-Changed-By: rearnsha State-Changed-When: Fri Jan 31 15:25:26 2003 State-Changed-Why: The latest compiler generates sub sp, sp, #4 lsl r0, r0, #2 mov r3, sp ldr r0, [r0, r3] add sp, sp, #4 bx lr http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=8159