From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12758 invoked by alias); 17 Feb 2003 22:06:01 -0000 Mailing-List: contact gcc-prs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-prs-owner@gcc.gnu.org Received: (qmail 12737 invoked by uid 71); 17 Feb 2003 22:06:01 -0000 Date: Mon, 17 Feb 2003 22:06:00 -0000 Message-ID: <20030217220601.12736.qmail@sources.redhat.com> To: nobody@gcc.gnu.org Cc: gcc-prs@gcc.gnu.org, From: Mark_Hamilton@3com.com Subject: Re: libstdc++/9697: invalid instruction Reply-To: Mark_Hamilton@3com.com X-SW-Source: 2003-02/txt/msg00740.txt.bz2 List-Id: The following reply was made to PR libstdc++/9697; it has been noted by GNATS. From: Mark_Hamilton@3com.com To: , , , , Mark Hamilton Cc: Subject: Re: libstdc++/9697: invalid instruction Date: Mon, 17 Feb 2003 14:04:53 -0800 I may have fixed my own bug. Is someone interested in verifying my fix. I'm not much of an assembly person. I've attached the files that I modified. To summarize the 68000 and 5200 processors do not support bsr.l. That I've verified from the appropriate manuals. The gcc m68k.md and m68k.h didn't take these into account. I modified m68k.md and m68k.h from the gcc-3.2.2 tar ball to check for 68000 and 5200. If so then jsr is used instead of bsr.l. The jsr instruction take an absolute value where as the bsr takes a relative address. The m68k.h needs to use the appropriate assembly for both PIC and non-PIC code. I posted a bug on this 9697. http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&p r=9697