From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26960 invoked by alias); 20 Feb 2003 12:13:24 -0000 Mailing-List: contact gcc-prs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-prs-owner@gcc.gnu.org Received: (qmail 26938 invoked by uid 48); 20 Feb 2003 12:13:24 -0000 Date: Thu, 20 Feb 2003 12:13:00 -0000 Message-ID: <20030220121324.26937.qmail@sources.redhat.com> To: gcc-bugs@gcc.gnu.org, gcc-prs@gcc.gnu.org, gertom@rgai.hu, nobody@gcc.gnu.org From: rearnsha@gcc.gnu.org Reply-To: rearnsha@gcc.gnu.org, gcc-bugs@gcc.gnu.org, gcc-prs@gcc.gnu.org, gertom@rgai.hu, nobody@gcc.gnu.org, gcc-gnats@gcc.gnu.org Subject: Re: target/9757: Gcc should use swp instruction in ARM targets X-SW-Source: 2003-02/txt/msg00987.txt.bz2 List-Id: Synopsis: Gcc should use swp instruction in ARM targets State-Changed-From-To: open->closed State-Changed-By: rearnsha State-Changed-When: Thu Feb 20 12:13:24 2003 State-Changed-Why: No, the SWP instruction should not be used. For several reasons. 1) It's very slow on some processors, since it forces an external bus access even if the data is already in the cache. 2) It's behaviour is not defined if access is made to a MMU managed page that is non-cacheable/bufferable. http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=9757