Dear contributor, our automatic CI has detected problems related to your patch(es).  Please find some details below.  If you have any questions, please follow up on linaro-toolchain@lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel.

We appreciate that it might be difficult to find the necessary logs or reproduce the issue locally. If you can't get what you need from our CI within minutes, let us know and we will be happy to help.

We track this report status in https://linaro.atlassian.net/browse/GNU-1132 , please let us know if you are looking at the problem and/or when you have a fix.

In gcc_check master-arm after:

  | commit gcc-14-8492-g1a8261e047f
  | Author: Richard Sandiford <richard.sandiford@arm.com>
  | Date:   Mon Jan 29 12:33:08 2024 +0000
  | 
  |     vect: Tighten vect_determine_precisions_from_range [PR113281]
  |     
  |     This was another PR caused by the way that
  |     vect_determine_precisions_from_range handles shifts.  We tried to
  |     narrow 32768 >> x to a 16-bit shift based on range information for
  |     the inputs and outputs, with vect_recog_over_widening_pattern
  |     (after PR110828) adjusting the shift amount.  But this doesn't
  | ... 36 lines of the commit log omitted.

FAIL: 3 regressions

regressions.sum:
		=== gcc tests ===

Running gcc:gcc.target/arm/simd/simd.exp ...
FAIL: gcc.target/arm/simd/mve-vshr.c scan-assembler-times vneg.s[0-9]+\\tq[0-9]+, q[0-9]+ 6
FAIL: gcc.target/arm/simd/mve-vshr.c scan-assembler-times vshl.s[0-9]+\\tq[0-9]+, q[0-9]+ 3
FAIL: gcc.target/arm/simd/mve-vshr.c scan-assembler-times vshl.u[0-9]+\\tq[0-9]+, q[0-9]+ 3

		=== Results Summary ===

You can find the failure logs in *.log.1.xz files in
 - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1636/artifact/artifacts/00-sumfiles/ .
The full lists of regressions and progressions are in
 - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1636/artifact/artifacts/notify/ .
The list of [ignored] baseline and flaky failures are in
 - https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1636/artifact/artifacts/sumfiles/xfails.xfail .

The configuration of this build is:
CI config tcwg_gcc_check master-arm

-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:

Current build   : https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1636/artifact/artifacts
Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1635/artifact/artifacts

Reproduce last good and first bad builds: https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/1a8261e047f7a2c2b0afb95716f7615cba718cd1/tcwg_gcc_check/master-arm/reproduction_instructions.txt

Full commit : https://github.com/gcc-mirror/gcc/commit/1a8261e047f7a2c2b0afb95716f7615cba718cd1

List of configurations that regressed due to this commit :
* tcwg_gcc_check
** master-arm
*** FAIL: 3 regressions
*** https://git-us.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/1a8261e047f7a2c2b0afb95716f7615cba718cd1/tcwg_gcc_check/master-arm/details.txt
*** https://ci.linaro.org/job/tcwg_gcc_check--master-arm-build/1636/artifact/artifacts