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[88.99.136.175]) by smtp.gmail.com with ESMTPSA id k1-20020a5d5181000000b0024207478de3sm29477026wrv.93.2023.01.02.14.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 14:56:40 -0800 (PST) From: ci_notify@linaro.org X-Google-Original-From: linaro-infrastructure-errors@lists.linaro.org Date: Mon, 2 Jan 2023 22:56:39 +0000 (UTC) To: Florian Weimer Cc: gcc-regression@gcc.gnu.org Message-ID: <2112020829.10869.1672700200836@jenkins.jenkins> Subject: [TCWG CI] Failure after basepoints/gcc-13-4953-g3b6cac2b44b: Compute a table of DWARF register sizes at compile MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_10868_652772220.1672700200125" X-Jenkins-Job: TCWG Build tcwg_gcc_bootstrap/master-aarch64-bootstrap X-Jenkins-Result: SUCCESS List-ID: X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org ------=_Part_10868_652772220.1672700200125 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Failure after basepoints/gcc-13-4953-g3b6cac2b44b: Compute a table of DWARF= register sizes at compile: Results changed to -10 # true: 0 # build_abe binutils: 1 # build_abe bootstrap: # FAILED # First few build errors in logs: # 00:04:03 /home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/snapshots/gcc.gi= t~master/libgcc/unwind-dw2.c:1579:3: error: this operation requires the SVE= ISA extension # 00:04:03 /home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/snapshots/gcc.gi= t~master/libgcc/unwind-dw2.c:1579:3: internal compiler error: Segmentation = fault # 00:04:04 /home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/snapshots/gcc.gi= t~master/libgcc/unwind-dw2.c:1579:3: error: this operation requires the SVE= ISA extension # 00:04:04 /home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/snapshots/gcc.gi= t~master/libgcc/unwind-dw2.c:1579:3: internal compiler error: Segmentation = fault # 00:04:04 make[3]: *** [/home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/sn= apshots/gcc.git~master/libgcc/shared-object.mk:14: unwind-dw2.o] Error 1 # 00:04:05 make[3]: *** [/home/tcwg-buildslave/workspace/tcwg_gnu_15/abe/sn= apshots/gcc.git~master/libgcc/shared-object.mk:17: unwind-dw2_s.o] Error 1 # 00:04:22 make[2]: *** [Makefile:20149: all-stage1-target-libgcc] Error 2 # 00:04:22 make[1]: *** [Makefile:25638: stage1-bubble] Error 2 # 00:04:22 make: *** [Makefile:1080: all] Error 2 from -10 # true: 0 # build_abe binutils: 1 # build_abe bootstrap: 2 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCT= ION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-6= 92 . Status of basepoints/gcc-13-4953-g3b6cac2b44b commit for tcwg_gcc_bootstrap= : commit 3b6cac2b44b384cd2091eaeaebeb3478c253a25d Author: Florian Weimer Date: Mon Jan 2 16:18:02 2023 +0100 Compute a table of DWARF register sizes at compile =20 The sizes are compile-time constants. Create a vector with them, so that they can be inspected at compile time. =20 gcc/ =20 * dwarf2cfi.cc (init_return_column_size): Remove. (init_one_dwarf_reg_size): Adjust. (generate_dwarf_reg_sizes): New function. Extracted from expand_builtin_init_dwarf_reg_sizes. (expand_builtin_init_dwarf_reg_sizes): Call generate_dwarf_reg_sizes. * target.def (init_dwarf_reg_sizes_extra): Adjust hook signature. * config/msp430/msp430.cc (msp430_init_dwarf_reg_sizes_extra): Adjust. * config/rs6000/rs6000.cc (rs6000_init_dwarf_reg_sizes_extra): Likewise. * doc/tm.texi: Update. * master-aarch64-bootstrap ** Failure after basepoints/gcc-13-4953-g3b6cac2b44b: Compute a table of DW= ARF register sizes at compile: ** https://ci.linaro.org/job/tcwg_gcc_bootstrap-build-master-aarch64-bootst= rap/1935/ Bad build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-build-master-aarch= 64-bootstrap/1935/artifact/artifacts Good build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-build-master-aarch= 64-bootstrap/1933/artifact/artifacts Reproduce current build: mkdir -p investigate-gcc-3b6cac2b44b384cd2091eaeaebeb3478c253a25d cd investigate-gcc-3b6cac2b44b384cd2091eaeaebeb3478c253a25d # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_gcc_bootst= rap-build-master-aarch64-bootstrap/1935/artifact/artifacts/manifest.sh --fa= il curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_gcc_boots= trap-build-master-aarch64-bootstrap/1933/artifact/artifacts/manifest.sh --f= ail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_gnu-build.sh ^^ true %%rr[top_artifacts] a= rtifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_gnu-build.sh ^^ true %%rr[top_artifacts] = artifacts) Full commit (up to 1000 lines): commit 3b6cac2b44b384cd2091eaeaebeb3478c253a25d Author: Florian Weimer Date: Mon Jan 2 16:18:02 2023 +0100 Compute a table of DWARF register sizes at compile =20 The sizes are compile-time constants. Create a vector with them, so that they can be inspected at compile time. =20 gcc/ =20 * dwarf2cfi.cc (init_return_column_size): Remove. (init_one_dwarf_reg_size): Adjust. (generate_dwarf_reg_sizes): New function. Extracted from expand_builtin_init_dwarf_reg_sizes. (expand_builtin_init_dwarf_reg_sizes): Call generate_dwarf_reg_sizes. * target.def (init_dwarf_reg_sizes_extra): Adjust hook signature. * config/msp430/msp430.cc (msp430_init_dwarf_reg_sizes_extra): Adjust. * config/rs6000/rs6000.cc (rs6000_init_dwarf_reg_sizes_extra): Likewise. * doc/tm.texi: Update. --- gcc/config/msp430/msp430.cc | 11 +----- gcc/config/rs6000/rs6000.cc | 14 +------ gcc/doc/tm.texi | 7 ++-- gcc/dwarf2cfi.cc | 93 ++++++++++++++++++++++-------------------= ---- gcc/target.def | 8 ++-- 5 files changed, 58 insertions(+), 75 deletions(-) diff --git a/gcc/config/msp430/msp430.cc b/gcc/config/msp430/msp430.cc index 6c15780a2b6..dbea8d7f50f 100644 --- a/gcc/config/msp430/msp430.cc +++ b/gcc/config/msp430/msp430.cc @@ -3202,11 +3202,9 @@ msp430_expand_eh_return (rtx eh_handler) #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA #define TARGET_INIT_DWARF_REG_SIZES_EXTRA msp430_init_dwarf_reg_sizes_extr= a void -msp430_init_dwarf_reg_sizes_extra (tree address) +msp430_init_dwarf_reg_sizes_extra (poly_uint16 *sizes) { int i; - rtx addr =3D expand_normal (address); - rtx mem =3D gen_rtx_MEM (BLKmode, addr); =20 /* This needs to match msp430_unwind_word_mode (above). */ if (!msp430x) @@ -3218,12 +3216,7 @@ msp430_init_dwarf_reg_sizes_extra (tree address) unsigned int rnum =3D DWARF2_FRAME_REG_OUT (dnum, 1); =20 if (rnum < DWARF_FRAME_REGISTERS) -=09{ -=09 HOST_WIDE_INT offset =3D rnum * GET_MODE_SIZE (QImode); - -=09 emit_move_insn (adjust_address (mem, QImode, offset), -=09=09=09 gen_int_mode (4, QImode)); -=09} +=09sizes[rnum] =3D 4; } } =20 diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 6ac3adcec6b..875684a3895 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23860,27 +23860,17 @@ rs6000_initial_elimination_offset (int from, int = to) /* Fill in sizes of registers used by unwinder. */ =20 static void -rs6000_init_dwarf_reg_sizes_extra (tree address) +rs6000_init_dwarf_reg_sizes_extra (poly_uint16 *sizes) { if (TARGET_MACHO && ! TARGET_ALTIVEC) { int i; - machine_mode mode =3D TYPE_MODE (char_type_node); - rtx addr =3D expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL= ); - rtx mem =3D gen_rtx_MEM (BLKmode, addr); - rtx value =3D gen_int_mode (16, mode); =20 /* On Darwin, libgcc may be built to run on both G3 and G4/5. =09 The unwinder still needs to know the size of Altivec registers. */ =20 for (i =3D FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) -=09{ -=09 int column =3D DWARF_REG_TO_UNWIND_COLUMN -=09=09(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); -=09 HOST_WIDE_INT offset =3D column * GET_MODE_SIZE (mode); - -=09 emit_move_insn (adjust_address (mem, mode, offset), value); -=09} +=09sizes[i] =3D 16; } } =20 diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 8fe49c2ba3d..b6d7900f212 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -9840,13 +9840,14 @@ used to return a smaller mode than the raw mode to = prevent call clobbered parts of a register altering the frame register size @end deftypefn =20 -@deftypefn {Target Hook} void TARGET_INIT_DWARF_REG_SIZES_EXTRA (tree @var= {address}) +@deftypefn {Target Hook} void TARGET_INIT_DWARF_REG_SIZES_EXTRA (poly_uint= 16 *@var{sizes}) If some registers are represented in Dwarf-2 unwind information in multiple pieces, define this hook to fill in information about the sizes of those pieces in the table used by the unwinder at runtime. -It will be called by @code{expand_builtin_init_dwarf_reg_sizes} after +It will be called by @code{generate_dwarf_reg_sizes} after filling in a single size corresponding to each hard register; -@var{address} is the address of the table. +@var{sizes} is the address of the table. It will contain +@code{DWARF_FRAME_REGISTERS} elements when this hook is called. @end deftypefn =20 @deftypefn {Target Hook} bool TARGET_ASM_TTYPE (rtx @var{sym}) diff --git a/gcc/dwarf2cfi.cc b/gcc/dwarf2cfi.cc index 1c70bd83f28..4d2bd869a4b 100644 --- a/gcc/dwarf2cfi.cc +++ b/gcc/dwarf2cfi.cc @@ -36,7 +36,7 @@ along with GCC; see the file COPYING3. If not see =20 #include "except.h"=09=09/* expand_builtin_dwarf_sp_column */ #include "profile-count.h"=09/* For expr.h */ -#include "expr.h"=09=09/* init_return_column_size */ +#include "expr.h"=09=09/* expand_normal, emit_move_insn */ #include "output.h"=09=09/* asm_out_file */ #include "debug.h"=09=09/* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ #include "flags.h"=09=09/* dwarf_debuginfo_p */ @@ -241,18 +241,6 @@ expand_builtin_dwarf_sp_column (void) return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); } =20 -/* MEM is a memory reference for the register size table, each element of - which has mode MODE. Initialize column C as a return address column. = */ - -static void -init_return_column_size (scalar_int_mode mode, rtx mem, unsigned int c) -{ - HOST_WIDE_INT offset =3D c * GET_MODE_SIZE (mode); - HOST_WIDE_INT size =3D GET_MODE_SIZE (Pmode); - emit_move_insn (adjust_address (mem, mode, offset), -=09=09 gen_int_mode (size, mode)); -} - /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and init_one_dwarf_reg_size to communicate on what has been done by the latter. */ @@ -274,17 +262,14 @@ struct init_one_dwarf_reg_state use for the size entry to initialize, and INIT_STATE is the communicati= on datastructure conveying what we're doing to our caller. */ =20 -static -void init_one_dwarf_reg_size (int regno, machine_mode regmode, -=09=09=09 rtx table, machine_mode slotmode, -=09=09=09 init_one_dwarf_reg_state *init_state) +static void +init_one_dwarf_reg_size (int regno, machine_mode regmode, +=09=09=09 poly_uint16 *table, +=09=09=09 init_one_dwarf_reg_state *init_state) { const unsigned int dnum =3D DWARF_FRAME_REGNUM (regno); const unsigned int rnum =3D DWARF2_FRAME_REG_OUT (dnum, 1); const unsigned int dcol =3D DWARF_REG_TO_UNWIND_COLUMN (rnum); - =20 - poly_int64 slotoffset =3D dcol * GET_MODE_SIZE (slotmode); - poly_int64 regsize =3D GET_MODE_SIZE (regmode); =20 init_state->processed_regno[regno] =3D true; =20 @@ -298,34 +283,22 @@ void init_one_dwarf_reg_size (int regno, machine_mode= regmode, init_state->wrote_return_column =3D true; } =20 - /* ??? When is this true? Should it be a test based on DCOL instead? *= / - if (maybe_lt (slotoffset, 0)) - return; - - emit_move_insn (adjust_address (table, slotmode, slotoffset), -=09=09 gen_int_mode (regsize, slotmode)); + table[dcol] =3D GET_MODE_SIZE (regmode); } =20 -/* Generate code to initialize the dwarf register size table located - at the provided ADDRESS. */ +/* Fill SIZES with size information for each DWARF register. */ =20 -void -expand_builtin_init_dwarf_reg_sizes (tree address) +static void +generate_dwarf_reg_sizes (poly_uint16 *sizes) { - unsigned int i; - scalar_int_mode mode =3D SCALAR_INT_TYPE_MODE (char_type_node); - rtx addr =3D expand_normal (address); - rtx mem =3D gen_rtx_MEM (BLKmode, addr); - - init_one_dwarf_reg_state init_state; + for (unsigned int i =3D 0; i < DWARF_FRAME_REGISTERS; i++) + sizes[i] =3D poly_uint16{}; =20 + init_one_dwarf_reg_state init_state{}; memset ((char *)&init_state, 0, sizeof (init_state)); =20 - for (i =3D 0; i < FIRST_PSEUDO_REGISTER; i++) + for (unsigned int i =3D 0; i < FIRST_PSEUDO_REGISTER; i++) { - machine_mode save_mode; - rtx span; - /* No point in processing a register multiple times. This could hap= pen =09 with register spans, e.g. when a reg is first processed as a piece of =09 a span, then as a register on its own later on. */ @@ -333,11 +306,11 @@ expand_builtin_init_dwarf_reg_sizes (tree address) if (init_state.processed_regno[i]) =09continue; =20 - save_mode =3D targetm.dwarf_frame_reg_mode (i); - span =3D targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); + machine_mode save_mode =3D targetm.dwarf_frame_reg_mode (i); + rtx span =3D targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)= ); =20 if (!span) -=09init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); +=09init_one_dwarf_reg_size (i, save_mode, sizes, &init_state); else =09{ =09 for (int si =3D 0; si < XVECLEN (span, 0); si++) @@ -345,19 +318,45 @@ expand_builtin_init_dwarf_reg_sizes (tree address) =09 rtx reg =3D XVECEXP (span, 0, si); =20 =09 init_one_dwarf_reg_size -=09=09(REGNO (reg), GET_MODE (reg), mem, mode, &init_state); +=09=09(REGNO (reg), GET_MODE (reg), sizes, &init_state); =09 } =09} } =20 if (!init_state.wrote_return_column) - init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); + sizes[DWARF_FRAME_RETURN_COLUMN] =3D GET_MODE_SIZE (Pmode); =20 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN - init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); + sizes[DWARF_ALT_FRAME_RETURN_COLUMN] =3D GET_MODE_SIZE (Pmode); #endif =20 - targetm.init_dwarf_reg_sizes_extra (address); + if (targetm.init_dwarf_reg_sizes_extra !=3D nullptr) + targetm.init_dwarf_reg_sizes_extra (sizes); +} + +/* Generate code to initialize the dwarf register size table located + at the provided ADDRESS. */ + +void +expand_builtin_init_dwarf_reg_sizes (tree address) +{ + poly_uint16 *sizes =3D XALLOCAVEC (poly_uint16, DWARF_FRAME_REGISTERS); + generate_dwarf_reg_sizes (sizes); + + scalar_int_mode mode =3D SCALAR_INT_TYPE_MODE (char_type_node); + rtx addr =3D expand_normal (address); + rtx mem =3D gen_rtx_MEM (BLKmode, addr); + for (unsigned int i =3D 0; i < DWARF_FRAME_REGISTERS; ++i) + { + unsigned short value; + if (sizes[i].is_constant (&value) && value =3D=3D 0) +=09/* No need to set the value to zero again. */ +=09continue; + + HOST_WIDE_INT offset =3D i * GET_MODE_SIZE (mode); + emit_move_insn (adjust_address (mem, mode, offset), +=09=09 gen_int_mode (sizes[i], mode)); + } } =20 =0C diff --git a/gcc/target.def b/gcc/target.def index db8af0cbe81..da5dd31d7a4 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4039,11 +4039,11 @@ DEFHOOK "If some registers are represented in Dwarf-2 unwind information in\n\ multiple pieces, define this hook to fill in information about the\n\ sizes of those pieces in the table used by the unwinder at runtime.\n\ -It will be called by @code{expand_builtin_init_dwarf_reg_sizes} after\n\ +It will be called by @code{generate_dwarf_reg_sizes} after\n\ filling in a single size corresponding to each hard register;\n\ -@var{address} is the address of the table.", - void, (tree address), - hook_void_tree) +@var{sizes} is the address of the table. It will contain\n\ +@code{DWARF_FRAME_REGISTERS} elements when this hook is called.", + void, (poly_uint16 *sizes), nullptr) =20 /* Fetch the fixed register(s) which hold condition codes, for targets where it makes sense to look for duplicate assignments to ------=_Part_10868_652772220.1672700200125--